MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 1322

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

P–P
Index-14
latency timer, 17-36, 17-54, 17-59
memory map/register definition, 17-11
memory space addressing, 17-47
modes of operation, 17-4
overview, 17-2
performance monitor events
POR configuration, 17-67
power management
register descriptions
signals summary, 17-6
target-abort termination, 17-53
target-disconnect cycles, 17-4, 17-53
agent configuration lock mode, 17-68
agent mode, 17-68
cache wrap mode, 17-47
host mode, 17-68
linear incrementing, 17-47
PCI-X mode
common events, 20-21
special-cycle operations, 17-64
configuration header registers, 17-30–17-42, 17-59
memory-mapped registers, 17-11
see also Signals, PCI/PCI-X
selection (POR), 4-19
32-bit memory base address register, 17-37
64-bit high memory base address register, 17-38
64-bit low memory base address register, 17-37
arbiter configuration register (PBACR), 17-42
base address registers, 17-36–17-38
base class code register, 17-35
bus function register (PBFR), 17-41
bus status register, 17-32, 17-49, 17-53, 17-65, 17-66
cache line size register, 17-35
capabilities pointer register, 17-39
command register, 17-31, 17-59
configuration and status register base address
device ID register, 17-31, 17-39
interrupt line register, 17-39
interrupt pin register, 17-40
latency timer register, 17-36
maximum grant (MAX GNT) register, 17-40
maximum latency (MAX LAT) register, 17-41
programming interface register, 17-34
revision ID register, 17-34
subclass code register, 17-35
vendor ID register, 17-30, 17-38
ATMU inbound registers, 17-19–17-23
ATMU outbound registers, 17-16–17-19
by acronym, see Register Index
configuration access registers, 17-14–17-15, 17-60
error management registers, 17-23–17-29
(PCSRBAR), 17-36
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
PCI_AD[47:40] signals as GP I/O, see Global utilities,
PCI_AD[63:0] (PCI address/data bus) signals, 17-6
PCI_C/BE [7:0] (PCI command/byte enable) signals, 17-7,
PCI_DEVSEL (PCI device select) signal, 17-7, 17-48
PCI_FRAME (PCI frame) signal, 17-7, 17-45
PCI_GNT[4:0] (PCI bus grant) signals, 17-8, 17-43
PCI_IDSEL (PCI initialization device) signal, 17-8
PCI_IRDY (PCI intitiator ready) signal, 17-8, 17-45
PCI_PAR (PCI parity) signal, 17-9
PCI_PERR (PCI parity error) signal, 17-9, 17-66
PCI_REQ[4:0] (PCI bus request) signals, 17-9, 17-42
PCI_SERR (PCI system error) signal, 17-10, 17-66
PCI_STOP (PCI stop) signal, 17-10, 17-49
PCI_TRDY (PCI target ready) signal, 17-10, 17-45, 17-52
Performance monitor (device)
target-initiated termination
transactions
turnaround cycle, 17-49
block diagram, 20-2
burstiness, 20-14, 20-28
control registers, 20-5–20-10
counters (PMCn)
event counting, 20-12
events, 20-16–20-27
target-abort error, 17-53
target-disconnect, 17-4, 17-53
fast back-to-back transactions, 17-56
interrupt-acknowledge transactions, 17-63
read transactions, 17-50
retry transactions, 17-53
special-cycle transactions, 17-64
timing diagrams, 17-50
transaction termination, 17-52
write transactions, 17-50, 17-51
general-purpose I/O signals
17-46, 17-48, 17-49, 17-65
chaining, 20-13
registers, 20-10
triggering, 20-13
chaining, 20-27
DDR controller, 20-17
debug, 20-27
DMA controller, 20-18
DUART, 20-27
e500 coherency module (ECM), 20-19
interrupt controller (PIC), 20-20
bus status register, termination status, 17-54
completion, 17-53
master-abort termination, 17-53
master-initiated, 17-52
target-initiated, 17-53, 17-54
timeout, 17-53
Freescale Semiconductor
Index