MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 1222

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Device Performance Monitor
20.4.8
Table 20-12
The settings in
For simple event counting, a non-threshold event is selected in PMLCAn[EVENT] and all other features
are disabled by clearing all register fields except for CE.
For the triggering example any event can be selected in PMLCAn[EVENT]. All other features are disabled
by clearing these register fields except for CE to allow interrupt signalling. If PMLCBn[TRIGONSEL] is
3 and PMLCBn[TRIGOFFSEL] is 5, the counter begins and ends counting based on the conditions in
counters three and five. Furthermore, if PMLCBn[TRIGONCNTL] is 1, the counter begins counting when
PMC3 changes value. According to the setting in PMLCBn[TRIGOFFCNTL], the counter ends counting
when PMC5 overflows. Also, although the register settings for PMC5 is not shown, PMLCAn[CE] for this
counter must be cleared so that interrupt signalling is not enabled and the counter does not freeze when it
overflows.
For threshold counting, a threshold event must be specified in PMLCAn[EVENT]. For this example, the
duration threshold value is scaled by two because PMLCBn[TBMULT] is one. All other features are
disabled by clearing the appropriate fields.
Any non-threshold event can use the burstiness feature. For burstiness counting, values for
PMLCAn[BSIZE,BGRAN,BDIST] and PMLCBn[TBMULT] must be specified.
20-28
•
•
•
•
Register
PMGC0
Simple event performance monitoring example
Triggering event performance monitoring example
Threshold event performance monitoring example
Burstiness event performance monitoring example
Performance Monitor Examples
contains sample register settings for the four supported modes.
PMGC0[FCECE]
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
PMGC0[PMIE]
PMGC0[FAC]
PMLCA n [CE]
Table 20-11
PMLCA n [FC]
Register Field
Field
FCECE
PMIE
FAC
Table 20-12. Register Settings for Counting Examples
are identical for all four examples.
Setting
Table 20-11. PMGC0 and PMLCA n Settings
0
1
1
0
1
Counters must not be frozen.
Performance monitor interrupts are enabled
Counters should be frozen when an interrupt is signalled.
Counters cannot be frozen for counting.
Overflow condition enable is required to allow interrupt signalling.
Simple Event
0
1
1
Triggering
0
1
1
Reason
Threshold
0
1
1
Freescale Semiconductor
Burstiness
0
1
1