MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 762

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Enhanced Three-Speed Ethernet Controllers
Table 15-10
15-32
20–24
0–15
Bits
16
17
18
19
25
26
27
28
CLRCNT Clear all statistics counters
AUTOZ
R100M
GMIIM
Name
STEN
FIFM
TBIM
RPM
describes the fields of the ECNTRL register.
—
—
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reserved
FIFO mode enable. If this bit is set, 8-bit FIFO interface mode is enabled. This bit can be pin configured
at reset to set or clear. See
0 Interface to external signals via the Ethernet MAC.
1 Interface to external signals via the 8-bit FIFO interface, bypassing the Ethernet MAC. Frame parsing
0 Allow MIB counters to continue to increment.
1 Reset all MIB counters.
This bit is self-resetting.
Automatically zero MIB counter values.
0 The user must write the addressed counter zero after a host read.
1 The addressed counter value is automatically cleared to zero after a host read.
This is a steady state signal and must be set prior to enabling the Ethernet controller and must not be
changed without proper care.
MIB counter statistics enabled.
0 Statistics not enabled
1 Enables internal counters to update
This is a steady state signal and must be set prior to enabling the Ethernet controller and must not be
changed without proper care.
Reserved
GMII interface mode. If this bit is set, a PHY with a GMII or RGMII interface is expected to be connected.
If cleared, a PHY with an MII or RMII interface is expected. The user should then set
MACCFG2[I/F Mode] accordingly. The state of this status bit is defined during power-on reset. See
Section 4.4.3, “Power-On Reset Configuration.”
0 MII or RMII mode interface expected
1 GMII or RGMII mode interface expected
Ten-bit interface mode. If this bit is set, ten-bit interface mode is enabled. This bit can be pin-configured
at reset to set or clear. See
0 GMII or MII or RMII mode interface
1 TBI mode interface
Reduced-pin mode for Gigabit interfaces. If this bit is set, a reduced-pin interface is expected on either
Ethernet and FIFO interfaces. RPM and RMM are never set together. This register can be
pin-configured at reset to 0 or 1. See
0 GMII or MII or TBI in non-reduced-pin mode configuration
1 RGMII or RTBI reduced-pin mode
RGMII/RMII 100 mode. This bit is ignored unless RPM or RMM are set and MACCFG2[I/F Mode] is
assigned to 10/100 (01). If this bit is set, the eTSEC interface is in 100 Mbps speed.
0 RGMII is in 10 Mbps mode;
1 RGMII is in 100 Mbps mode;
in this mode automatically assumes that IP packets are being received and transmitted. See
FIFOCFG register for configuration of the FIFO interface.
FIFO configured for 8-bit operation
RMII is in 10 Mbps mode, and every 10th RMII Reference clock is used to transfer data
RMII is in 100 Mbps mode, and data is transferred on every Reference clock
Table 15-10. ECNTRL Field Descriptions
Section 4.4.3, “Power-On Reset
Section 4.4.3, “Power-On Reset Configuration.”
Section 4.4.3, “Power-On Reset
Description
Configuration.”
Configuration.”
Freescale Semiconductor