MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 948

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

DMA Controller
16.3.1.2
The status registers, shown in
transfer.
16-12
Offset 0x104
Reset
Bits
26
27
28
29
30
31
W
R
0x184
0x204
0x284
0
CDSM/
SWSM
Name
CTM
XFE
CA
CC
CS
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Status Registers (SR n )
0 Disable the new chaining features.
1 Enable the new chaining features.
0 No effect
1 Cause the current transfer to be aborted and SR n [CB] to be cleared if the channel is busy. The channel
0 Configure the channel in chaining mode.
1 Configure the channel into direct mode. This means that software is responsible for placing all the
read when continuing a transfer. This bit is reserved for external master mode.
0 No effect
1 The DMA transfer restarts the transferring process starting at the current descriptor address.
master start enable mode.
0 Halt the DMA process if channel is busy (SR n [CB] is set). No effect if the channel is not busy.
1 Start the DMA process if channel is not busy (CB is cleared). If the channel was halted (CS = 0 and CB
Extended features enable
Channel abort
Channel transfer mode
Channel continue. This bit applies only to chaining mode and is cleared by hardware after the first descriptor
Channel start. This bit is also automatically set by hardware during single-write start mode and external
• In chaining mode: current descriptor start mode/single-write start mode
• In direct mode: Setting this bit and MR n [SRW] causes a write to the source address register to
simultaneously set MR n [CS], starting a DMA transfer. Clearing this bit and setting MR n [SRW] causes a
write to the destination address register to simultaneously set MR n [CS], starting a DMA transfer. This bit
must be cleared when MR n [SRW] is cleared.
remains in the idle state until a new transfer is programmed.
required parameters into necessary registers to start the DMA process.
= 1), the transfer continues from the point at which it was halted.
— In basic mode (MR n [XFE] is cleared), setting this bit causes a write to the current link
— In extended chaining mode (MR n [XFE] is set), setting this bit causes a write to the current list
descriptor address register to simultaneously set MR n [CS], starting a DMA transfer.
descriptor address register to simultaneously set MR n [CS], starting a DMA transfer.
Table 16-5. MR n Field Descriptions (continued)
Figure
—
Figure 16-5. Status Registers (SR n )
16-5, report various DMA conditions during and after a DMA
All zeros
Description
23
w1c
TE
24
—
25
CH PE EOLNI CB
26
w1c
27
w1c
28
Freescale Semiconductor
29
EOSI
Access: Mixed
w1c
30
EOLSI
w1c
31