MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 23

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Paragraph
Number
13.3.1.11
13.3.1.12
13.3.1.13
13.4
13.4.1
13.4.1.1
13.4.1.2
13.4.1.3
13.4.1.4
13.4.2
13.4.3
13.4.4
13.4.4.1
13.4.4.2
13.4.4.3
13.4.5
13.4.5.1
13.4.5.2
13.4.5.3
13.5
14.1
14.1.1
14.1.2
14.1.3
14.1.3.1
14.1.3.2
14.1.4
14.2
14.3
14.3.1
14.3.1.1
14.3.1.2
14.3.1.2.1
14.3.1.2.2
14.3.1.2.3
14.3.1.2.4
14.3.1.3
Freescale Semiconductor
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Functional Description................................................................................................. 13-19
DUART Initialization/Application Information .......................................................... 13-24
Introduction.................................................................................................................... 14-1
External Signal Descriptions ......................................................................................... 14-4
Memory Map/Register Definition ................................................................................. 14-8
Serial Interface......................................................................................................... 13-20
Baud-Rate Generator Logic ..................................................................................... 13-21
Local Loopback Mode ............................................................................................. 13-22
Errors ....................................................................................................................... 13-22
FIFO Mode .............................................................................................................. 13-22
Overview.................................................................................................................... 14-2
Features...................................................................................................................... 14-2
Modes of Operation ................................................................................................... 14-3
Power-Down Mode.................................................................................................... 14-4
Register Descriptions............................................................................................... 14-10
Scratch Registers (USCR0, USCR1) ................................................................... 13-17
Alternate Function Registers (UAFR0, UAFR1) (ULCR[DLAB] = 1) .............. 13-17
DMA Status Registers (UDSR0, UDSR1) .......................................................... 13-18
START Bit ........................................................................................................... 13-20
Data Transfer ....................................................................................................... 13-21
Parity Bit .............................................................................................................. 13-21
STOP Bit.............................................................................................................. 13-21
Framing Error ...................................................................................................... 13-22
Parity Error .......................................................................................................... 13-22
Overrun Error....................................................................................................... 13-22
FIFO Interrupts .................................................................................................... 13-23
DMA Mode Select ............................................................................................... 13-23
Interrupt Control Logic........................................................................................ 13-23
LBC Bus Clock and Clock Ratios ......................................................................... 14-3
Source ID Debug Mode ......................................................................................... 14-4
Base Registers (BR0–BR7) ................................................................................. 14-10
Option Registers (OR0–OR7).............................................................................. 14-12
UPM Memory Address Register (MAR)............................................................. 14-17
Address Mask .................................................................................................. 14-12
Option Registers (ORn)—GPCM Mode ......................................................... 14-13
Option Registers (ORn)—UPM Mode ............................................................ 14-15
Option Registers (ORn)—SDRAM Mode ...................................................... 14-16
Local Bus Controller
Contents
Chapter 14
Title
Number
Page
xxiii