MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 688

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Local Bus Controller
Special care must be taken in the following cases:
14.4.4.4.7
The address lines can be controlled by the pattern the user provides in the UPM. The address multiplex
bits can choose between driving the transaction address, driving it according to the multiplexing specified
by the MxMR[AM] field, or driving the MAR contents on the address signals. In all cases, LA[27:31] of
the LBC are driven by the five lsbs of the address selected by AMX, regardless of whether the NA bit of
the RAM word is used to increment the current address. The effect of NA = 1 is visible only when
AMX = 00 chooses the column address.
Table 14-30
AMX = 10. The 16 msbs of the LAD[0:31] bus during an address phase are driven with zero in the
AMX = 10 case.
Note that any change to the AMX field from one RAM word to the next RAM word executed results in an
address phase on the LAD[0:31] bus with the assertion of LALE for the number of cycles set for LALE in
the ORn and LCRR registers. The LGPL[0:5] signals maintain the value specified in the RAM word
during the LALE phase.
14-70
000 Signal driven
001
010
011
100
101
AM
•
•
•
•
•
on external
signal when
address
multiplexing is
enabled—
RAM word
AMX = 10
LAD[0:31] as
When UTA and REDO are set together, TA is asserted the number of times specified by the REDO
function.
When NA and REDO are set together, the address is incremented the number of times specified by
the REDO function.
When LOOP and REDO are set together, the loop mechanism works as usual and the line is
repeated according to the REDO function.
LAST and REDO must not be set together.
REDO should not be used within the exception routine.
Address
Signals
shows how MxMR[AM] settings affect address multiplexing when the RAM word
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Address Multiplexing (AMX)
A0–A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31
0
0
0
0
0
0
A8
A7
A6
A5
A4
A3
A9
A8
A7
A6
A5
A4
Table 14-30. UPM Address Multiplexing
A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23
A9
A8
A7
A6
A5
A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22
A9
A8
A7
A6
A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21
A9
A8
A7
A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20
A9
A8
A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
A9
A10 A11 A12 A13 A14 A15 A16 A17 A18
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