MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 767

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Freescale Semiconductor
21–26
Bits
18
19
20
27
28
RFC_PAUSE Receive flow control pause frame (written by the eTSEC). This read-only status bit is set if a flow control
TFC_PAUSE Transmit flow control pause frame. Set this bit to transmit a PAUSE frame. If this bit is set, the MAC stops
TUCSEN
VLINS
Name
THDF
—
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
TCP/UDP header checksum generation enable. When set, the eTSEC offloads TCP or UDP header
checksum generation. See
0 TCP or UDP header checksum generation is disabled even if enabled in a transmit frame control block.
1 TCP or UDP header checksum generation is performed as determined by the settings in the current
VLAN (IEEE Std. 802.1Q) tag insertion enable. Applicable only for transmission via the Ethernet MAC.
0 Do not insert a VLAN tag into the frame.
1 Insert a VLAN tag into the frame. If the frame FCB has a valid VLAN field, use the FCB to source the
Transmit half-duplex flow control under software control for 10-/100-Mbps half-duplex media. This bit is
not self-resetting.
0 Disable back pressure
1 Back pressure is applied to media by raising carrier
Reserved
pause frame was received and the transmitter is paused for the duration defined in the received pause
frame. This bit automatically clears after the pause duration is complete.
0 Pause duration complete.
1 Flow control pause frame received.
transmission of data frames after the current transmission completes. Next, the GTSC interrupt in the
IEVENT register is asserted. With transmission of data frames stopped, the MAC transmits a MAC
control PAUSE frame with the duration value obtained from the PTV register. The TXC interrupt occurs
after sending the control pause frame. Next, the MAC clears TFC_PAUSE and resumes transmitting data
frames. Note that if the transmitter is paused due to user assertion of GTS or reception of a PAUSE
frame, the MAC may still transmit a MAC control PAUSE frame.
0 MAC continues.
1 Pause frame is transmitted.
transmit frame control block.
VLAN control word, otherwise take the default VLAN control word from register DFVLAN.
Table 15-15. TCTRL Field Descriptions (continued)
Section 15.6.4.2, “Transmit Path Off-Load,” on page
Description
Enhanced Three-Speed Ethernet Controllers
15-158.
15-37