MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 728

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Local Bus Controller
Synchronous Burst Write
Figure 14-89
The DSI samples HA, HDST, HCID, HD, HWBE, HRDE, and HBRST on the first HCLKIN rising edge
on which HCS is asserted. If HCID[0:3] match the CHIPID value, the DSI is accessed. HWBE are
asserted, HBRST is asserted, and HRDE is negated. Assertion of HTA indicates that the DSI is ready to
complete the current beat of the access and the host must proceed to the next beat of this access. When the
host reaches the last beat of the access, it must terminate the burst access. Typically HTA is asserted
immediately for each beat of the access. If the write buffer is full, HTA assertion is delayed. Because HTA
is connected to the LUPWAIT signal of the UPM, all local bus signals are frozen until HTA goes to 0 and
then the UPM continues in its pattern. After the last beat of the access, HTA is driven to logic 1 and stops
being driven on the next rising edge of HCLKIN. The host can start its next access to the same MSC8102
immediately in the next HCLKIN rising edge without negating HCS between accesses. If the next access
is not to the same MSC8102, then, to prevent contention on HTA, the host must wait to access the next
device until the previous DSI stops driving HTA. The easiest way to achieve this is to insert idle cycles at
the end of the UPM pattern to guarantee that HTA is inactive.
14-110
HWBE[0:7]
Legend:
HDST[0:1]
Timing conventions:
HA[11:29]
HCID[0:3]
1
0
1
0
HD[0:63]
HCLKIN
HBRST
HRDE
HCS
shows a synchronous burst write access.
HTA
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Valid value that can be 1 or 0
Don’t care
Three-state output signal that is not driven by the DSI
Figure 14-89. Synchronous Burst Write to MSC8102 DSI
D(A)
A
D(A+1)
D(A+2)
n = 3 in 64-bit data bus interface
n = 7 in 32-bit data bus interface
D(A+2)
D(A+ n )
Freescale Semiconductor