MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 475

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

11.5.4
A data transfer ends with a STOP condition generated by the master device. A master transmitter can
generate a STOP condition after all the data has been transmitted.
If a master receiver wants to terminate a data transfer, it must inform the slave transmitter by not
acknowledging the last byte of data (by setting the transmit acknowledge bit (I2CCR[TXAK])) before
reading the next-to-last byte of data. At this time, the next-to-last byte of data has already been transferred
on the I
For 1-byte transfers, a dummy read should be performed by the interrupt service routine (see
Section 11.5.8, “Interrupt Service Routine
byte of data, a STOP condition must first be generated.
The I
must be set before allowing the I
I2CCR[TXAK] needs to be cleared again for subsequent I
setting up the I2CCR for the next transfer.
11.5.5
At the end of a data transfer, if the master still wants to communicate on the bus, it can generate another
START condition followed by another slave address without first generating a STOP condition. This is
accomplished by setting I2CCR[RSTA].
11.5.6
It is sometimes necessary to force the I
(even though SDA may already be driven, which indicates that the bus is busy). This can occur when a
system reset does not cause all I
while this I
be used to force this I
11.5.7
In the slave interrupt service routine, the module addressed as a slave should be tested to check if a calling
of its own address has been received. If I2CSR[MAAS] is set, software should set the transmit/receive
mode select bit (I2CCR[MTX]) according to the R/W command bit (I2CSR[SRW]). Writing to I2CCR
clears MAAS automatically. MAAS is read as set only in the interrupt handler at the end of that address
cycle where an address match occurred; interrupts resulting from subsequent data transfers clear MAAS.
A data transfer can then be initiated by writing to I2CDR for slave transmits or dummy reading from
I2CDR in slave-receive mode. The slave drives SCL low between byte transfers. SCL is released when the
I2CDR is accessed in the required mode.
Freescale Semiconductor
1. Disable the I
2. Enable the I
3. Read the I2CDR
4. Return the I
2
C controller automatically generates a STOP if I2CCR[TXAK] is set. Therefore, I2CCR[TXAK]
2
C interface, so the last byte will not receive the data acknowledge (because I2CCR[TXAK] is set).
2
C module is coming out of reset and will stay low indefinitely. The following procedure can
Generation of STOP
Generation of Repeated START
Generation of SCL When SDA Low
Slave Mode Interrupt Service Routine
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
2
2
2
C module to slave mode by setting I2CCR to 0x80
C module by setting I2CCR to 0xA0
2
C module and set the master bit by setting I2CCR to 0x20
C module to generate SCL so that the device driving SDA can finish its transaction:
2
C devices to be reset. Thus, SDA can be driven low by another I
2
C module to receive the last data byte on the I
2
C module to become the I
Flowchart”). Before the interrupt service routine reads the last
2
C transactions. This can be accomplished when
2
C bus master out of reset and drive SCL
2
C bus. Eventually,
I
2
2
C Interfaces
C device
11-23