MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 50

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Figure
Number
10-13
10-14
10-15
10-16
10-17
10-18
10-19
10-20
10-21
10-22
10-23
10-24
10-25
10-26
10-27
10-28
10-29
10-30
10-31
10-32
10-33
10-34
10-35
10-36
10-37
10-38
10-39
10-40
10-41
10-42
10-43
10-44
10-45
10-46
10-47
10-48
11-1
11-2
11-3
11-4
11-5
l
Global Timer Base Count Register (GTBCRn)................................................................... 10-23
Global Timer Vector/Priority Register (GTVPRn).............................................................. 10-24
Global Timer Destination Registers (GTDRn).................................................................... 10-25
Example Calculation for Cascaded Timers......................................................................... 10-26
Timer Control Register (TCR) ............................................................................................ 10-26
External Interrupt Summary Register (ERQSR)................................................................. 10-28
IRQ_OUT Summary Register 0 (IRQSR0) ........................................................................ 10-28
IRQ_OUT Summary Register 1 (IRQSR1) ........................................................................ 10-29
IRQ_OUT Summary Register 2 (IRQSR2) ........................................................................ 10-29
Critical Interrupt Summary Register 0 (CISR0) ................................................................. 10-30
Critical Interrupt Summary Register 1 (CISR1) ................................................................. 10-30
Critical Interrupt Summary Register 2 (CISR2) ................................................................. 10-31
Performance Monitor n Mask Registers 0 (PMnMR0)....................................................... 10-31
Performance Monitor n Mask Registers 1 (PMnMR1)....................................................... 10-32
Performance Monitor n Mask Registers 2 (PMnMR2)....................................................... 10-33
Message Registers (MSGRs) .............................................................................................. 10-33
Message Enable Register (MER) ........................................................................................ 10-34
Message Status Register (MSR).......................................................................................... 10-34
Shared Message Signaled Interrupt Register (MSIRs) ....................................................... 10-35
Shared Message Signaled Interrupt Status Register (MSISR)............................................ 10-36
Shared Message Signaled Interrupt Index Register (MSIIR) ............................................. 10-36
Shared Message Signaled Interrupt Vector/Priority Register (MSIVPRn)......................... 10-37
Shared Message Signaled Interrupt Destination Registers (MSIDRn) ............................... 10-37
External Interrupt Vector/Priority Registers (EIVPR0–EIVPR11) ..................................... 10-38
External Interrupt Destination Registers (EIDRs) .............................................................. 10-39
Internal Interrupt Vector/Priority Registers (IIVPRs) ......................................................... 10-40
Internal Interrupt Destination Registers (IIDRs) ................................................................ 10-41
Messaging Interrupt Vector/Priority Registers (MIVPRs).................................................. 10-42
Messaging Interrupt Destination Registers (MIDRs) ......................................................... 10-43
Per-CPU Register Address Decoding in a Four-Core Device............................................. 10-44
Interprocessor Interrupt Dispatch Registers (IPIDR0–IPIDR3) ......................................... 10-45
Processor Current Task Priority Register (CTPR) .............................................................. 10-45
Processor Who Am I Register (WHOAMI)........................................................................ 10-46
Processor Interrupt Acknowledge Register (IACK) ........................................................... 10-46
End of Interrupt Register (EOI) .......................................................................................... 10-47
PIC Interrupt Processing Flow Diagram ............................................................................. 10-48
I
I
I
I
I
2
2
2
2
2
C Block Diagram................................................................................................................ 11-1
C Address Register (I2CADR)........................................................................................... 11-6
C Frequency Divider Register (I2CFDR) .......................................................................... 11-6
C Control Register (I2CCR)............................................................................................... 11-7
C Status Register (I2CSR) ................................................................................................. 11-9
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
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