MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 1164
MPC8533EVTARJ
Manufacturer Part Number
MPC8533EVTARJ
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8533VTALF.pdf
(112 pages)
2.MPC8533VTALF.pdf
(2 pages)
3.MPC8533VTALF.pdf
(16 pages)
4.MPC8533VTALF.pdf
(1332 pages)
Specifications of MPC8533EVTARJ
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
1.067GHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
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Global Utilities
19.4.1
This section describes the global utilities registers in detail.
19.4.1.1
PORPLLSR, shown in
cfg_core_pll[0:1], and cfg_pci_clk POR configuration pins. See
Section 4.4.3.2, “e500 Core PLL Ratio,”
19-4
0xE_00C0 LBCVSELCR—LBC voltage select control register
0xE_00A0 PVR—Processor version register
0xE_00A4 SVR—System version register
0xE_00B0 RSTCR—Reset control register
0xE_0B20 DDRCSR—DDR configuration status register
0xE_0B24 DDRCDR—DDR control driver register
0xE_0B28 DDRCLKDR—DDR clock disable register
0xE_0E00 CLKOCR—Clock out control register
0xE_0F04 SRDS1CR1—SerDes 1 control register 1
0xE_0F10 SRDS2CR1—SerDes 2 control register 1
0xE_0040 GPOUTDR—General-purpose output data register
0xE_0050 GPINDR—General-purpose input data register
0xE_0060 PMUXCR—Alternate function signal multiplex control
0xE_0070 DEVDISR—Device disable control
0xE_0080 POWMGTCSR—Power management status and control register
0xE_0090 MCPSUMR—Machine check summary register
0xE_0094 RSTRSCR—Reset request status and control register
Offset
Register Descriptions
POR PLL Status Register (PORPLLSR)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 19-3. Global Utilities Block Register Summary (continued)
Figure
19-1, contains the settings for the PLL ratios as set by the cfg_sys_pll[0:3],
Interrupt and Reset Status and Control Registers
Register
Power Management Registers
Status and Control Registers
for more information.
Version Registers
Device Disables
Section 4.4.3.1, “System PLL
Access
Mixed
Mixed
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
w1c
R
R
R
R
e500 processor
0x0000_0000
0x0000_0000
0x0000_0000
0x nnnn _0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x1100_4418
0x1100_4418
MPC8533E
version
system
version
Reset
Freescale Semiconductor
19.4.1.10/19-13
19.4.1.11/19-13
19.4.1.12/19-14
19.4.1.13/19-16
19.4.1.14/19-17
19.4.1.15/19-18
19.4.1.16/19-18
19.4.1.17/19-19
19.4.1.18/19-20
19.4.1.19/19-20
19.4.1.20/19-21
19.4.1.21/19-21
19.4.1.22/19-22
19.4.1.23/19-23
19.4.1.24/19-24
19.4.1.25/19-25
19.4.1.9/19-12
Section/page
Ratio,” and
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