MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 1069

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MPC8533EVTARJ

Manufacturer Part Number
MPC8533EVTARJ
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MPC8533EVTARJ

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
1.067GHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

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18.3.5.1.2
The PCI Express outbound translation extended address registers, shown in
most-significant bits of a 64 bit translation address.
Table 18-16
18.3.5.1.3
The PCI Express outbound window base address registers, shown in
for the windows which are translated to the external address space. Addresses for outbound transactions
are compared to these windows. If such a transaction does not fall within one of these spaces the
transaction is forwarded through a default register set.
Freescale Semiconductor
12–31
0–11
Bits
Offset Window 0: 0xC04
Offset Window 1: 0xC28
Reset
Reset
Name
TEA
Figure 18-16. PCI Express Outbound Window Base Address Registers (PEXOWBAR n )
W
W
R
R
describes the fields of the PCI Express outbound translation extended address registers.
Window 1: 0xC24
Window 2: 0xC44
Window 3: 0xC64
Window 4: 0xC84
Window 2: 0xC48
Window 3: 0xC68
Window 4: 0xC88
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
0
0
PCI Express Outbound Translation Extended Address Registers
(PEXOTEAR n )
PCI Express Outbound Window Base Address Registers
(PEXOWBAR n )
Reserved
Translation extended address. System address which indicates the starting point of the outbound translated
address. The translation address must be aligned based on the size field. Corresponds to PCI Express
address bits [63:44].
Figure 18-15. PCI Express Outbound Translation Extended Address
Table 18-16. PCI Express Outbound Extended Address Translation
7
8
WBEA
Register n Field Descriptions
Registers (PEXOTEAR n )
11 12
11 12
All zeros
All zeros
Description
Figure
WBA
TEA
18-16, select the base address
Figure
PCI Express Interface Controller
Access: Read/Write
Access: Read/Write
18-15, contain the
31
31
18-21

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