MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 195

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

5.4
The e500 implements the following instructions:
Freescale Semiconductor
•
•
The embedded category instruction set for 32-bit implementations. This is composed primarily of
the user-level instructions defined by the Power Architecture user instruction set architecture
(UISA). The e500 does not include floating-point instructions that require floating-point registers
(FPRs), load string, or store string instructions.
The e500 supports the following instructions:
— Integer select. Now part of the base category. Consists of the Integer Select instruction (isel),
— Performance monitor.
— Cache locking. Consists of the instructions described in
— Machine check. Defines the Return from Machine Check Interrupt instruction (rfmci).
— SPE vector instructions. Vector instructions are defined that view the 64-bit GPRs as composed
— The embedded floating-point categories provide scalar and vector floating-point instructions.
Instruction Set
which functions as an if
comparison to a CR bit. This instruction eliminates conditional branches, decreases latency,
and reduces the code footprint.
of a vector of two 32-bit elements (some instructions also read or write 16-bit elements). Some
scalar instructions produce a 64-bit scalar result.
Scalar single-precision floating-point instructions use only the lower 32 bits of the GPRs;
double-precision operands (e500v2 only) use all 64 bits.
floating-point instructions.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Move from Performance Monitor Register
Move to Performance Monitor Register
Data Cache Block Lock Clear
Data Cache Block Touch and Lock Set
Data Cache Block Touch for Store and Lock Set
Instruction Cache Block Lock Clear
Instruction Cache Block Touch and Lock Set
Unless otherwise indicated, references to e500 apply to both e500v1 and
e500v2.
Table 5-2. Performance Monitor Instructions
Table 5-2
Table 5-3. Cache Locking Instructions
-
then-else statement that selects between two source registers by
Name
Name
lists performance monitor instructions.
NOTE
Mnemonic
Mnemonic
dcbtstls
mfpmr
mtpmr
Table
dcbtls
icbtls
dcblc
icblc
Table 5-4
5-3.
lists embedded
CT, rA, rB
CT, rA, rB
CT, rA, rB
CT, rA, rB
CT, rA, rB
rD,PMRN
PMRN,rS
Syntax
Syntax
Core Complex Overview
5-11