MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 1155

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

18.4.2.1.3
Software can generate outbound assert or deassert INTx message transactions by using the outbound
ATMU mechanism described in
18.4.2.1.4
Host software has to set up the MSI capability registers to enable MSI mode, and have the correct values
for the MSI address and data register. Then local software has to read the MSI address in the MSI
capability register and configure the outbound ATMU window to map the translated address to the MSI
address. Software has to determine the number of allocated messages in the MSI capability register and
allocates the appropriate data values to use. A write to the ATMU window containing the MSI address with
the appropriate data value will generate the desired MSI transaction to the remote RC.
18.4.2.2
18.4.2.2.1
MSIs are the preferred interrupt signaling mechanism for PCI Express. However, in RC mode, the PCI
Express controller supports the INTx virtual-wire interrupt signaling mechanism (as described in the PCI
Express specification). Whenever the controller receives an inbound INTx (INTA, INTB, INTC, or INTD)
asserted or negated message, it asserts or negates an equivalent internal INTx signal (inta, intb, intc, or
intd) to the PIC.
The internal INTx signals from the PCI Express controller are logically combined with the interrupt
request (IRQn) input signals so that they share the same interrupt controlled by the associated EIVPRn and
EIDRn registers in the PIC. Refer to
information about handling of PCI Express INTx interrupts and the external interrupt request (IRQn)
signals.
If a PCI Express INTx interrupt is being used, then the PIC must be configured so that external interrupts
are active-low (EIVPRn[P] = 0), and level-sensitive (EIVPRn[S] = 1).
18.4.2.2.2
An inbound MSI cycle must hit into the PCSRBAR window with the address offset that points to the
MSIIR register in the PIC. Note that it is the responsibility of the host software to configure each EP’s MSI
capability registers such that an MSI cycle generated from the EP device is routed to the MSIIR register
in the PIC and for the appropriate interrupt to be generated to the core.
18.4.3
To prevent overflowing of the receiver’s buffers and for ordering compliance purposes, the transmitter
cannot send transactions unless it has enough flow control (FC) credits to send. Each device maintains an
FC credit pool. The FC information is conveyed between the two link partners by DLLPs during link
training (initial credit advertisement). The transaction layer performs the FC accounting functions. One FC
unit is four DWs (16-bytes) of data.
Freescale Semiconductor
Initial Credit Advertisement
RC Handling of INTx Message and MSI Interrupt
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Software INTx Message Generation
Software MSI Generation
INTx Message Handling
MSI Handling
Section 18.4.1.8.1, “Outbound ATMU Message
Chapter 10, “Programmable Interrupt
Controller,” for more
PCI Express Interface Controller
Generation.”
18-107