MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 677

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Figure 14-53
The following events initiate a UPM cycle:
The RAM array contains 64 words of 32-bits each. The signal timing generator loads the RAM word from
the RAM array to drive the general-purpose lines, byte-selects, and chip-selects. If the UPM reads a RAM
word with WAEN set, the external LUPWAIT signal is sampled and synchronized by the memory
controller and the current request is frozen.
14.4.4.1
A special pattern location in the RAM array is associated with each of the possible UPM requests. An
internal device’s request for a memory access initiates one of the following patterns (MxMR[OP] = 00):
Freescale Semiconductor
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Any internal device requests an external memory access to an address space mapped to a
chip-select serviced by the UPM
A UPM refresh timer expires and requests a transaction, such as a DRAM refresh
A bus monitor time-out error during a normal UPM cycle redirects the UPM to execute an
exception sequence
Read single-beat pattern (RSS)
Read burst cycle pattern (RBS)
Write single-beat pattern (WSS)
Write burst cycle pattern (WBS)
LUPWAIT
shows the basic operation of each UPM.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
If the LGPL4/LGTA/LUPWAIT/LPBSE signal is used as both an input and
an output, a weak pull-up is required. Refer to the hardware specification for
details regarding termination options.
Memory Access Request
UPM Requests
Figure 14-53. User-Programmable Machine Functional Block Diagram
(issued in software)
Exception Request
Internal / External
Run Command
Timer Request
UPM Refresh
Request
Logic
Wait
Hold
Generator
WAEN Bit
Index
Array
NOTE
(LAST = 0)
Increment
Index
Index
Internal Controls
Internal
Signals
Latch
RAM Array
Generator
Signals
Timing
LGPL n
LBS n
LCS n
Local Bus Controller
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