MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 988

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

PCI Bus Interface
17-10
PCI_SERR
PCI_STOP
PCI_TRDY
Signal
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 17-2. PCI Interface Signals—Detailed Signal Descriptions (continued)
I/O
I/O PCI system error.The PCI system error signal is both an input and output signal on this PCI controller.
I/O Stop.The stop signal is both an input and output signal on this PCI controller.
I/O Target ready. Both an input and output signal on this PCI controller.
O As outputs for the bidirectional PCI system error, these signals operate as described below.
O As outputs for the bidirectional stop, these signals operate as described below.
O As outputs for the bidirectional target ready, these signals operate as described below.
I As inputs for the bidirectional PCI system error, these signals operate as described below.
I As inputs for the bidirectional stop, these signals operate as described below.
I As inputs for the bidirectional target ready, these signals operate as described below.
Meaning
Meaning
Meaning
Meaning
Meaning
Meaning
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2
State
State
State
State
State
State
Asserted—Indicates that an address parity error, a target-abort (when this PCI controller is
Negated—Indicates no error.
Asserted—Indicates that a target (other than this PCI controller) has detected a
Negated—Indicates no error.
Asserted—Indicates that this PCI controller, acting as a PCI target, is requesting that the
Negated—Indicates that the current transaction can continue.
Asserted—Indicates that a target is requesting that the PCI initiator stop the current
Negated—Indicates that the current transaction can continue.
Asserted—Indicates that this PCI controller, acting as a PCI target, can complete the
Negated—Indicates that the PCI initiator needs to wait before this PCI controller, acting as
Asserted—Another PCI target is able to complete the current data phase of a transaction.
Negated—Indicates a wait cycle from another target.
acting as the initiator), or some other system error (where the result is a catastrophic
error) was detected.
catastrophic error.
initiator stop the current transaction.
transaction.
current data phase of a PCI transaction. During a read, this PCI controller asserts
PCI_TRDY to indicate that valid data is present on the data bus. During a write, this
PCI controller asserts PCI_TRDY to indicate that it is prepared to accept data.
a PCI target, can complete the current data phase. During a read, this PCI controller
negates PCI_TRDY to insert a wait cycle when it cannot provide valid data to the
initiator. During a write, this PCI controller negates PCI_TRDY to insert a wait cycle
when it cannot accept data from the initiator.
Description
Freescale Semiconductor