MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 379

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MPC8533EVTARJ

Manufacturer Part Number
MPC8533EVTARJ
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MPC8533EVTARJ

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
1.067GHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

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9.5.4.1
Freescale Semiconductor
If running with many devices, zero-delay PLL clock buffers, JEDEC-JESD82 standard, should be
used. These buffers were designed for DDR applications.
A 72 bit x 64 Mbytes DDR bank has 9-byte-wide DDR chips, resulting in 18 DDR chips in a
two-bank system. In this case, each MCK/MCK signal pair should drive exactly three devices.
PCB traces for DDR clock signals should be short, all on the same layer, and of equal length and
loading.
DDR SDRAM manufacturers provide detailed information on PCB layout and termination issues.
SDRAM Clock
Clock Distribution
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
MDQ[0:63]
MDM[0:7]
MDQS
MCS0
MCS1
MRAS
MCAS
MWE
Figure 9-40. DDR SDRAM 4-Beat Burst Write Timing—ACTTORW = 4
MA n
ROW
0
1
ACTTORW
ROW
2
3
COL
4
D0
5
D1 D2 D3
COL
6
D0
7
D1 D2
COL
8
D3
00
D0
9
D1 D2 D3
COL
10
11
D0
DDR Memory Controller
D1 D2
12
D
9-57

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