MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 625

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Freescale Semiconductor
LAD[0:31]
LA[27:31]
LDP[0:3]
LGPL5
LBCTL
Signal
LCKE
I/O
I/O Multiplexed address/data bus. For configuration of a port size in BR n [PS] as 32 bits, all of LAD[0:31] must
I/O Local bus data parity. Drives and receives the data parity corresponding with the data phases on LAD[0:31].
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
O General-purpose line 5
O Data buffer control. The memory controller activates LBCTL for the local bus when a GPCM- or
O Local bus non-multiplexed address lsbs. All bits driven on LA[27:31] are defined for 8-bit port sizes. For
O Local bus clock enable
Table 14-2. Local Bus Controller Detailed Signal Descriptions (continued)
UPM-controlled bank is accessed. Access to an SDRAM machine-controlled bank does not activate the
buffer control. Buffer control is disabled by setting OR n [BCTLD].
32-bit port sizes, LA[30:31] are don’t cares; for 16-bit port sizes LA31 is a don’t care.
Meaning
Meaning
Meaning
Meaning
Meaning
Meaning
Timing Assertion/Negation—Drive and receive the data parity corresponding with the data phases on
Timing Assertion/Negation—During assertion of LALE, LAD[0:31] are driven with the RAM address for
State
State
State
State
State
State
be connected to the external RAM data bus, with LAD[0:7] occupying the most significant byte lane
(at address offset 0). For a port size of 16 bits, LAD[0:7] connect to the most significant byte lane (at
address offset 0), while LAD[8:15] connect to the least-significant byte lane (at address offset 1);
LAD[16:31] are unused for 16-bit port sizes. For a port size of 8 bits, only LAD[0:7] are connected to
the external RAM.
Asserted/Negated—One of six general-purpose signals when in UPM mode, and drives a value
Asserted/Negated—The LBCTL signal normally functions as a write/read control for a bus
Asserted/Negated—Although the LBC shares an address and data bus, up to five lsbs of the
Asserted/Negated—LAD[0:31] is the shared 32-bit address/data bus through which external
Asserted/Negated—During write accesses, a parity bit is generated for each 8 bits of LAD[0:31],
Asserted/Negated—LCKE is the bus clock enable signal (CKE) for JEDEC-standard SDRAM
programmed in the UPM array.
transceiver connected to the LAD lines. Note that an external data buffer must not drive the
LAD lines in conflict with the LBC when LBCTL is high, because LBCTL remains high after
reset and during address phases.
RAM address always appear on the dedicated address signals, LA[27:31]. These may be
used, unlatched, in place of LAD[27:31] to connect the five lsbs of the address for address
phases. For some RAM devices, such as fast-page DRAM, LA[27:31] serve as the column
address offset during a burst access.
RAM devices transfer data and receive addresses.
the access to follow. External logic should propagate the address on LAD[0:31] while LALE
is asserted, and latch the address upon negation of LALE. After LALE is negated,
LAD[0:31] are either driven by write data or are made high impedance by the LBC in order
to sample read data driven by an external device. Following the last data transfer of a write
access, LAD[0:31] are again taken into a high-impedance state.
such that LDP0 is even/odd parity for LAD[0:7], while LDP3 is even/odd parity for
LAD[24:31]. Unused byte lanes for port sizes less than 32 bits have undefined parity.
LAD[0:31]. For read accesses, the parity bits for each byte lane are sampled on LDP[0:3]
with the same timing that read data is sampled on LAD[0:31]. LDP[0:3] change impedance
in concert with LAD[0:31].
devices. Asserted during normal SDRAM operation.
Description
Local Bus Controller
14-7