MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 481

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

A block diagram of the SEC internal architecture is shown in
to transfer 64-bit words between the bus and any register inside the SEC.
An SEC operation begins when the host writes a descriptor pointer to the fetch FIFO in one of the four
SEC crypto-channels. From this point on, the channel directs the sequence of operations. The channel uses
the descriptor pointer to read the descriptor, then decodes the first word of the descriptor to determine the
operation to be performed and the crypto-execution units needed to perform it. The channel requests the
controller to assign the needed crypto-execution units. Next, the channel requests that the controller fetch
the keys, context, and data from locations specified in the rest of the descriptor. The controller satisfies the
requests by making requests to the master interface per the programmable priority scheme. Data is fed into
the execution units through their registers and input FIFOs. The execution units read from their input
FIFOs and write processed data to their output FIFOs. The channel requests the controller to write data
from the output FIFOs and registers, back to system memory via the master/slave interface.
The channel can signal to the host that it is done with a descriptor via interrupt or by a writeback of the
descriptor header into host memory. For more about this signaling, see
Freescale Semiconductor
Security Engine
Internal System Bus
Interface
Bus
(SEC)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Crypto-
channel
Crypto-
channel
Crypto-
channel
Crypto-
channel
eTSEC
Figure 12-1. SEC Connected to System Bus
Figure 12-2. SEC Functional Modules
eTSEC
Control
Coherency Module
eTSEC
PKEU
e500 Core
eTSEC
FIFO
FIFO
DEU
Figure
MDEU
FIFO
FIFO
OCEAN
L2 Cache
12-2. The controller block is designed
AESU
FIFO
FIFO
Section 12.5, “Crypto-Channels.”
DDR
Controller
AFEU
FIFO
FIFO
FIFO
FIFO
KEU
Security Engine (SEC) 2.1
System
Memory
FIFO
RNG
12-3