MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 738

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Enhanced Three-Speed Ethernet Controllers
15.4.1
Below is a description of the eTSEC interface signals. For RGMII mode details please refer to the
Hewlett-Packard reduced gigabit media-independent interface (RGMII) specification version 1.2a, dated
9/22/2000. RMII mode details follow the RMII Consortium Specification, dated 3/20/1998. All other
modes follow the IEEE 802.3 standard, 2000 Edition. Input signals not used are internally disabled. Except
for TSECn_GTX_CLK, output signals not used are driven low.
15-8
TSEC n _TXD[7:4]
TSEC n _TXD[3:0]
TSEC n _TX_CLK
TSEC n _TX_ER
TSEC n _TX_EN
Signal Name
Detailed Signal Descriptions
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 15-1. eTSEC n Network Interface Signal Properties (continued)
MII—transmit clock, input
TBI—PMA receive clock 1, input
RMII—reference transmit and receive clock, input
FIFO—transmit clock, input
RGMII, RTBI—unused
GMII—transmit data bit 7:4, output
TBI—transmit code group (TCG) bit 7:4, output
FIFO—transmit data bit 7:4, output
MII, RGMII, RTBI, RMII—unused, output driven zero
GMII, MII—Transmit data bits 3:0, output
TBI—TCG bits 3:0, output
RGMII (TX_CLK rising)—Transmit data bits 3:0, output
RGMII (TX_CLK falling)—Transmit data bits 7:4, output
RTBI (TX_CLK rising)—TCG bits 3:0, output
RTBI (TX_CLK falling)—TCG bits 8:5, output
RMII—TXD[1:0] transmit data bits, output
RMII—TXD[3:2] unused, output driven zeroFIFO—Transmit data bits 3:0, output
GMII, MII—transmit error, output
RGMII, RTBI, RMII—unused, output driven zero
TBI—TCG bit 9, output
FIFO—transmit error or transmit frame control bit, output
GMII, MII, RMII—Transmit data valid, output
TBI—TCG bit 8, output
RGMII (TX_CLK rising)—Transmit data enabled, output
RGMII (TX_CLK falling)—Transmit error, output
RTBI (TX_CLK rising)—TCG bit 4, output
RTBI (TX_CLK falling)—TCG bit 9, output
FIFO—Transmit data valid or transmit control bit, output
Function
Freescale Semiconductor
Reset
State
0000
0000
—
0
0