MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 302

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

L2 Look-Aside Cache/SRAM
disable register (L2ERRDIS[MBECCDIS, SBECCDIS]). See
Capture
remain enabled during the initialization process.
7.9.2
The L2 cache may be completely invalidated by setting the L2I bit of the L2 control register (L2CTL).
Note that no data is lost in this process because the L2 cache is a write-through cache and contains no
modified data. Flash invalidation of the cache is necessary when the cache is initially enabled and may be
necessary to recover from some error conditions such as a tag parity error.
The invalidation process requires several cycles to complete. The L2I bit remains set during this procedure
and is then cleared automatically when the procedure is complete. The L2 cache controller issues retries
for all transactions on the e500 core complex bus while the flash invalidation process is in progress.
Note that the contents of memory-mapped SRAM regions of the data array are unaffected by a flash
invalidation of the L2 cache regions of the array.
7.9.3
7.9.3.1
An individual soft error that causes a single- or multi-bit ECC error can be cleared from the L2 array
simply by performing a dcbf instruction on the address captured in the L2ERRADDR register. This will
invalidate the line in the L2 cache. When the load that caused the ECC error is performed again, the data
will be reallocated into the L2 with ECC bits set properly again.
If the threshold for single bit errors set in the L2ERRCTL register is exceeded, then the L2 cache should
be flash invalidated to clear out all single-bit errors.
Note that no data is lost by dcbfs or flash invalidates, since the L2 cache is write-through and contains no
modified data.
7.9.3.2
A tag parity error must be fixed by flash invalidating the L2 cache. Note that a dcbf operation to the
address that caused the error to be reported is not sufficient since a tag parity error is seen as an L2 miss
and will not cause invalidation of the bad tag. Proper L2 operation cannot be guaranteed if an L2 tag parity
error is not repaired by a flash invalidation of the entire array.
7.9.4
The L2 status array uses four bits for each line to determine the status of the line. Different combinations
of these bits result in different L2 states. The status bits are as follows:
7-34
•
•
Valid (V)
Instruction locked (IL)
Registers.” If the array is initialized by a DMA engine using cache-line writes, ECC checking can
Flash Invalidation of the L2 Cache
Managing Errors
L2 Cache States
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
ECC Errors
Tag Parity Errors
Section 7.3.1.4.2, “Error Control and
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