MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 567

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

12.4.7.12 KEU IV_2 Register (Fresh) (KEUIV2)
The fresh value, KEU IV_2 register, is used during the initialization phase of the 3GPP F9 algorithm. This
value is ignored when the F8 algorithm is selected. The fresh value must be written before a new message
to be processed with 3GPP F9 is started. After the initialization phase has been completed, KEU IV_2
register is no longer used during message processing. KEU IV_2 register need not be written during
context switches.
12.4.7.13 KEU Context Data Registers (KEUC n )
There are 6, 64-bit KEU context data registers that allow the host to read/write the contents of the context
used to process the message. The KEU context data registers must be read when changing context and
restored to their original values to resume processing an interrupted message. For F8 and 3GPP F9 modes,
all 6 64-bit KEU context data registers must be read to retrieve context, and all 6 must be written back to
restore context. The context must be written prior to the key data. If the any of the KEU context data
registers are written during message processing, a context error will be generated. All KEU context data
registers are cleared when a hard/soft reset or initialization is performed.
12.4.7.14 KEU Key Data Registers_1 and _2 (Confidentiality Key) (KEUKD n )
The first two KEU key data registers together hold one 128-bit key that is used for F8
encryption/decryption. KEU key data register_1, (CK-high), holds the first 8 bytes (1-8). KEU key data
register_2, (CK-low), holds the second 8 bytes (9-16). The KEU key data registers must be written before
message processing begins and cannot be written while the block is processing data, or a context error
occurs.
Reading from either of these registers results in an address error being reflected in the KEU interrupt status
register.
Freescale Semiconductor
Address 0x3_E110
Reset
W
R
0
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
In typical operation, a frame will be received and processed in it’s entirety,
with the KEU performing session specific initialization using the contexts
of KEU IV_1 and IV_2 registers. The KEU context data and IV_1 registers
should only be unloaded/reloaded when the processing of a frame is
discontinued prior to completion; then processing is resumed.
Figure 12-67. KEU IV_2 Register (Fresh)
KEU IV_2 Register (Fresh)
NOTE
All zeros
Security Engine (SEC) 2.1
Access: Read/write
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