MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 1250

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Debug Features and Watchpoint Facility
MECC[0:4] is all ones. A data-valid signal (DVAL) is driven on MECC5 during valid DDR SDRAM data
cycles.
21.4.3
If MSRCID0 is low when sampled during POR, the LBC is selected as the source for the debug
information appearing on MSRCID[0:4] and MDVAL. For more information on this mode, see
Section 14.1.3.2, “Source ID Debug Mode.”
21.4.4
The watchpoint monitor (WM) can be programmed to arm and trigger on many different events including
any of the following:
A watchpoint event can be used in the following ways:
The large counters available in the performance monitor block and the interlock between it and the
watchpoint monitor support sophisticated debug scenarios.
A WM trigger event may be composed of several events programmed in the watchpoint monitor control
registers (WMCR0–WMCR1). Because the watchpoint monitor is disabled by default during POR, these
registers must be initialized to make use of this debug feature. Note that the WM address mask register
(WMAMR) and the type mask register (WMTMR) are cleared during POR. This means that the
watchpoint monitor’s default behavior following a power-on reset is to trigger on any address and no
transaction type. The reset value of WMCR0[TMD] is 0 which means transaction matching is enabled but
since no transaction is selected (WMTMR=0), a match will never occur. Either the transaction matching
must be disabled by setting WMCR0[TMD] to a value of 1, or valid transactions must be selected by
setting one or more of the WMTMR bits to a value of 1.
21.4.4.1
The WM can produce a performance monitor (PM) event with every trigger. This is accomplished by
configuring the performance monitor to count WM events. For more information on this configuration see
the events named ‘Number of watchpoint monitor hits’ and ‘Number of trace buffer hits’ in
21-26
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External event (through TRIG_IN)
A trace buffer event
A performance monitor overflow event
A comparison of the current and programmed context ID registers
Trigger a logic analyzer (using TRIG_OUT)
Arm or trigger the trace buffer
Trigger a performance monitor event
Local Bus Interface Debug
Watchpoint Monitor
Watchpoint Monitor Performance Monitor Events
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
In this mode, MECC[0:5] must be disconnected from all SDRAM devices
to prevent contention on those lines.
NOTE
Freescale Semiconductor
Table
20-10.