MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 664

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Local Bus Controller
14.4.2.3
External access termination is supported by the GPCM using the asynchronous LGTA input signal, which
is synchronized and sampled internally by the local bus. If, during assertion of LCSn, the sampled LGTA
signal is asserted, it is converted to an internal generation of transfer acknowledge, which terminates the
current GPCM access (regardless of the setting of ORn[SETA]). LGTA should be asserted for at least one
bus cycle to be effective. Note that because LGTA is synchronized, bus termination occurs two cycles after
LGTA assertion, so in the case of a read cycle, the device still must drive data as long as LOE is asserted.
The user selects whether transfer acknowledge is generated internally or externally (LGTA) by
programming ORn[SETA]. Asserting LGTA always terminates an access, even if ORn[SETA] = 0
(internal transfer acknowledge generation), but it is the only means by which an access can be terminated
if ORn[SETA] = 1. The timing of LGTA is illustrated by the example in
14.4.2.4
Boot chip-select operation allows address decoding for a boot ROM before system initialization. LCS0 is
the boot chip-select output; its operation differs from other external chip-select outputs after a system reset.
When the core begins accessing memory after system reset, LCS0 is asserted for every local bus access
until BR0 or OR0 is reconfigured.
The boot chip-select also provides a programmable port size, which is configured during reset. The boot
chip-select does not provide write protection. LCS0 operates this way until the first write to OR0 and it
can be used as any other chip-select register after the preferred address range is loaded into BR0. After the
first write to OR0, the boot chip-select can be restarted only with a hardware reset.
the initial values of the boot bank in the memory controller.
14-46
LBCTL
LGTA
LCS n
LCLK
LALE
LAD
LOE
TA
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
A
External Access Termination (LGTA)
Boot Chip-Select Operation
Address
Figure 14-33. External Termination of GPCM Access
Latched Address
Read Data
Figure
14-33.
Table 14-25
Freescale Semiconductor
describes