MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 885

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

The receive timer threshold counter is reset to the value in RXIC[ICTT] and begins counting down on
receiving the frame following an interrupt.
15.6.3.11 Inter-Frame Gap Time
If a station must transmit, it waits until the LAN becomes silent for a specified period (inter-frame gap).
After a station begins sending, it continually checks for collisions on the LAN. If a collision is detected,
the station forces a jam signal (all ones) on its frame and stops transmitting. Collisions usually occur close
to the beginning of a packet. The station then waits a random time period (back-off) before attempting to
send again. After the back-off completes, the station waits for silence on the LAN and then begins
retransmission on the LAN. This process is called a retry. If the frame is not successfully sent within a
specified number of retries, an error is indicated.
The minimum inter-frame gap time for back-to-back transmission is 96 bit times. The receiver receives
back-to-back frames with this minimum spacing. In addition, after waiting a required number of bit times
(based on the back-off algorithm), the transmitter waits for carrier sense to be negated before
retransmitting the frame. Retransmission begins 36 bit times after carrier sense is negated for at least 60 bit
times.
15.6.3.12 Internal and External Loop Back
Setting MACCFG1[Loop Back] causes the MAC transmit outputs to be looped back to the MAC receive
inputs. Clearing this bit results in normal operation. This bit is cleared by default. Clearing this bit results
in normal operation.
15.6.3.13 Error-Handling Procedure
The eTSEC reports frame reception and transmission error conditions using the channel BDs, the error
counters, and the IEVENT register.
Transmission errors are described in
Freescale Semiconductor
Transmitter underrun
Retransmission
attempts limit expired
Late collision
Error
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Transmitter underrun can occur either after frame transmission has commenced, or in response to an
incomplete sequence of TxBDs. In the former case, the controller sends 32 bits that ensure a CRC
error, and terminates buffer transmission. In the latter case, the relevant transmit queue is halted. In
all cases, the eTSEC closes the buffer, sets TxBD[UN], IEVENT[XFUN], and IEVENT[TXE]. The
controller resumes transmission after TSTAT[THLT] is cleared (and DMACTRL[GTS] is cleared).
The controller terminates buffer transmission, sets TxBD[RL], closes the buffer, IEVENT[CRL], and
IEVENT[TXE]. Transmission resumes after TSTAT[THLT] is cleared (and DMACTRL[GTS] is cleared).
The controller terminates buffer transmission, sets TxBD[LC], closes the buffer, IEVENT[LC], and
IEVENT[TXE]. The controller resumes transmission after TSTAT[THLT] is cleared (and
DMACTRL[GTS] is cleared).
Table 15-137. Transmission Errors
Table
15-137.
Response
Enhanced Three-Speed Ethernet Controllers
15-155