MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 721

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Figure 14-82
The asynchronous SRAM-like mode of the DSI is inherently slower than the synchronous mode and
should be used, if only relatively small amounts of data are transferred between the communications
controller and the MSC8102. To allow for maximum timing flexibility, the UPM machine of the LBC
should be used.
The UPM programmer is responsible for ensuring correct setup and hold timings for all signals. The UPM
allows sufficient control to satisfy any requirements here.
Figure 14-83
on the first falling edge of the host write byte strobe signals (HWBS) on which the host chip select signal
(HCS) is asserted. If the HCID[0:3] signals match the CHIPID value, the DSI is accessed. The DSI will
signal with the assertion of the host transfer acknowledge signal (HTA), whether it is ready to sample the
host data bus (HD), and the host can terminate the access by immediately negating HWBS. The WAEN
feature of the UPM must be used to insert wait states while the DSI is busy. The UWPL bit in the MxMR
must be cleared to interpret the correct polarity of HTA. The DSI samples the host address bus (HA) and
the host data bus (HD) on the rising edge of HWBS. In addition the assertion of HWBS[0:3] are sampled
at the end and are part of the access attributes.
Because the UPM is used for this mode, the DCR[4]:HTAAD should be set to 1 and DCR[9–10]:HTADT
should be defined to a value different than 00. This mode is to be used in implementations with a pull-up
resistor on HTA. The host can start its next access (back-to-back accesses) without negating HCS between
accesses. If the next access is not to the same MSC8102, then to prevent contention on the HTA signal, the
host must wait until the previous DSI stops driving HTA before it accesses the next device. If the next
access is to the same MSC8102, the host must not start consecutive accesses before HTA is actively driven
to a value of 1 by the previous access. The easiest way to achieve this is to insert idle cycles at the end of
the UPM pattern to guarantee that HTA is inactive.
Freescale Semiconductor
shows an asynchronous write access. The DSI samples the host chip ID signals (HCID[0:3])
shows the interface to the MSC8102 DSI for asynchronous mode.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Local Bus Interface
Figure 14-82. Interface to MSC8102 DSI in Asynchronous Mode
LAD[0:31]
LUPWAIT
LA[27:29]
LBS[0:3]
LGPL2
LCS n
LALE
LCSy
INT n
Latch
HD[0:31]
HA[11:26]
HCID[0:3]
HA[27:29]
HRDS/HRDE
HWBS/HDBS/
HWBE/HDBE[0:3]
HTA
HINT
HBCS
HCS
MSC8102
Local Bus Controller
14-103