MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 790

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MPC8533EVTARJ

Manufacturer Part Number
MPC8533EVTARJ
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MPC8533EVTARJ

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
1.067GHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

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Enhanced Three-Speed Ethernet Controllers
15-60
0110
0111 0–15
1000 0–19
1001 0–28
1010 0–23
1011 0–23
PID
1
16–31
20–31
29–31
24–31
24–31
8–31
0–7
Bit
Name
TOS
SAL
ETY
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
L4P
VID
PRI
Reserved, should be written with zero.
Source MAC address, least significant 24 bits. Defaults to 0x000000.
Reserved, should be written with zero.
Ethertype of next layer protocol, i.e., last ethertype if layer 2 headers nest. Defaults to 0xFFFF.
Using the filer to match ETY does not work in the case of PPPoE packets, because the PPPoE ethertype
Instead, software should use PID=1 fields IP4 (ETY = 0x0021) and IP6 (ETY = 0x0057) to distinguish
Packets with a value in the length/type field greater than 1500 and less than 1536 are treated as payload
length. If the eTSEC is used in a network where there are packets carrying a type designation between
1500 and 1536 (note there are none currently publicly defined by IANA), then the S/W must confirm the
parser and filer results by checking the type/length field after the packet has been written to memory to
see if it falls in this range.
Note that the eTSEC filer gets multiple packet attributes as a result of parsing the packet. The behavior
of the eTSEC is that it will pull the innermost ethertype found in the packet; this means that in many
supported protocols, it is impossible to create a filer rule that will match on the outer ethertype. There
are four cases that need to be highlighted.
1. The jumbo ethertype (0x8870)—In this case, the eTSEC assumes that the following header is
2. The PPPoE ethertype described above.
3. The VLAN tag ethertype (0x8100)—In this case, one can use the PID1 VLN bit to indicate that the
4. The MPLS tagged packets. In this case, one can use arbitrary extraction bytes to compare to the
Reserved, should be written with zero.
VLAN network identifier (as per IEEE Std. 802.1Q). This value defaults to 0x000 if no VLAN tag was
found, or the VLAN tag contained only priority information.
Reserved, should be written with zero.
VLAN user priority (as per IEEE Std. 802.1p). This value defaults to 000 (best effort priority) if no VLAN
tag was found.
Reserved, should be written with zero.
IPv4 header Type Of Service field or IPv6 Traffic Class field. This value defaults to 0x00 (default RFC
2474 best-effort behavior) if no IP header appeared.
Note that for IPv6 the Traffic Class field is extracted using the IP header definition in RFC 2460. IPv6
headers formed using the earlier RFC 1883 have a different format and must be handled with software.
Reserved, should be written with zero.
Layer 4 protocol identifier as per published IANA specification. This is the last recognized protocol type
recognized in the case of IPv6 extension headers. This value defaults to 0xFF to indicate that no layer
4 header was recognized (possibly due to absence of an IP header).
in the original packet, 0x8864, is always overwritten with the PPP protocol field. Thus, matches on
ETY == 0x8864 always fail.
PPPoE session packets carrying IPv4 and IPv6 datagrams. Other PPP protocols are encoded in the
ETY field, but many of them overlap with real ethertype definitions. Consult IANA and IEEE for
possible ambiguities.
LLC/SNAP. LLC/SNAP has an associated etherype, and the ETY field will be populated with that
ethertype. This makes it impossible to file on jumbo frames.
In this case, one can use arbitrary extracted bytes to pull the outermost Ethertype.
packet had a VLAN tag.
actual ethertype if a filer rule is intending to file based on an MPLS label existence.
Table 15-33. RQFPR Field Descriptions (continued)
Description
Freescale Semiconductor

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