MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 1051

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

A transaction may be broken up into smaller sized transactions depending on the original request size,
transaction type, and either the PCI Express device control register [MAX_PAYLOAD_SIZE] field for
write requests or the PCI Express device control register [MAX_READ_SIZE] field for read requests. The
controller performs PCI Express ordering rule checking to determine which transaction is to be sent on the
PCI Express link.
In general, transactions are serviced in the order that they are received from the internal platform (OCeaN).
Only when there is a stalled condition does the controller apply PCI Express ordering rules to outstanding
transactions. For posted write transactions, once all data has been received from the internal platform
(OCeaN), the data is forwarded to the PCI Express link and the transaction is considered as done. For
non-posted write transactions, the controller waits for the completion packets to return before considering
the transaction finished. For non-posted read transactions, the controller waits for all completion packets
to return and then forwards all data back to the internal platform before terminating the transaction.
18.1.1.2
Inbound PCI Express transactions to internal platform are first mapped to a translation window to
determine what internal platform transactions are to be issued.
A transaction may be broken up into smaller sized transactions when sending to the internal platform
depending on the original request size, byte enables and starting/ending addresses. The controller performs
PCI Express ordering rule checking to determine what transaction is to be sent next to the internal platform
(OCeaN).
In general, transactions are serviced in the order that they are received from the PCI Express link. Only
when there is a stalled condition does the controller apply PCI Express ordering to outstanding
transactions. For posted write transactions, once all data has been received from the PCI Express link, the
data is forwarded to the internal platform and the transaction is considered as done. For non-posted read
transactions, the controller forwards internal platform data back to the PCI Express link.
Note that the controller splits transactions at the crossing of every 256-byte-aligned boundary when
sending data back to the PCI Express link.
18.1.2
The following is a list of features supported by the PCI Express controller:
Freescale Semiconductor
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Complies with the PCI Express™ Base Specification, Revision 1.0a
Supports root complex (RC) and endpoint (EP) configurations
32- and 64-bit address support
x4, x2 and x1 link support on SerDes 1; x1 link support on SerDes 2
Supports accesses to all PCI Express memory and I/O address spaces (requestor only)
Supports posting of processor-to-PCI Express and PCI Express-to-memory writes
Supports strong and relaxed transaction ordering rules
PCI Express configuration registers (type 0 in EP mode, type 1 in RC mode)
Baseline and advanced error reporting support
Features
Inbound Transactions
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
PCI Express Interface Controller
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