MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 959

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MPC8533EVTARJ

Manufacturer Part Number
MPC8533EVTARJ
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MPC8533EVTARJ

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
1.067GHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

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Table 16-18
16.3.1.13
The destination stride register contains the stride size, and distance. Note that the destination stride
information is loaded when a new list descriptor is read from memory. Therefore, the destination stride
register is applicable for all link descriptors in the new list. Changing the destination stride information for
a link requires that a new list be generated.
Table 16-19
Freescale Semiconductor
20–31
20–31
8–19
8–19
Offset 0x140
Offset 0x144
Reset
Bits
Reset
Bits
0–7
0–7
W
W
R
R
0x1C0
0x240
0x2C0
0x1C4
0x244
0x2C4
0
0
Name
Name
SSS
SSD
DSS
DSD
describes the fields of the SSRn.
describes the fields of the DSRn.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Destination Stride Registers (DSR n )
Reserved
Source stride size. Number of bytes to transfer before jumping to the next address as specified in the source
stride distance field.
Source stride distance. The source stride distance in bytes from start byte to start byte.
Reserved
Destination stride size. Number of bytes to transfer before jumping to the next address as specified in the
destination stride distance field.
Destination stride distance. The destination stride distance in bytes from start byte to start byte.
Figure 16-21. Destination Stride Registers (DSR n )
7
7
Figure 16-20. Source Stride Registers (SSR n )
8
8
Table 16-18. SSR n Field Descriptions
Table 16-19. DSR n Field Descriptions
Figure 16-21
DSS
SSS
All zeros
All zeros
Description
Description
describes the DSRn.
19 20
19 20
SSD
DSD
Access: Read/Write
Access: Read/Write
DMA Controller
16-23
31
31

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