MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 730

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Local Bus Controller
Note that broadcasting is allowed only for write accesses.
The DSI sets the DSI error register (DER) OVF bit if there is an overflow during broadcast accesses. This
bit can be cleared by writing a value of 1 to it.
To avoid data corruption, if DER[0]:OVF is set, no broadcast access is written until the bit is reset.
Therefore, after the last broadcast access, and before any regular write access, DER[0]:OVF must first be
read and reset if it is set.
In broadcast accesses, the host must comply with the following rules:
14-112
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In asynchronous mode, HWBS[0:3]/HDBS[0:3] assertion time should be at least the minimum,
which is defined in the AC characteristics section of the MSC8102 Technical Data sheet.
In synchronous mode single access, the host must wait 1 cycle before terminating the access.
Access signals must be in the same valid state during two positive edges of the host clock cycles.
Access duration is two clock cycles (the DSI may translate accesses lasting longer than two clock
cycles as two or more back-to-back accesses).
In synchronous mode burst accesses, broadcast accesses are not allowed.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
To avoid overflow when accessing DSI registers during broadcast accesses,
wait at least 10 host clock cycles in synchronous mode or 8 internal clock
cycles in asynchronous mode between each DSI register access.
In asynchronous mode, write data from a previous access (even a normal
write access) may be lost due to overflow during broadcast accesses. To
prevent such a loss, ensure that previous access data has propagated to the
FIFO or DSI registers, depending on the type of previous access. This can
be achieved by performing a read access prior to the first broadcast access.
NOTE
NOTE
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