MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 1326

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

S–S
Index-18
ARC Four execution unit (AFEU), 12-6
block diagram, 12-3
data encryption standard execution unit (DEU), 12-6,
descriptors, 12-4, 12-16
Diffie-Hellman key exchanges, 12-6
disabling the block, 12-115
ECC digital signatures, 12-6
error handling, 12-98, 12-103
execution units (EUs), 12-25
features, 12-1
interrupts, 12-103–12-104, 12-108
Kasumi execution unit (KEU), 12-8, 12-79
link tables, 12-102
memory map/register definition, 12-10
message digest execution unit (MDEU), 12-7, 12-50
overview
public key execution unit (PKEU), 12-5, 12-26
random number generator (RNG), 12-7, 12-62
context, 12-49
header dword, 12-17
pointer dwords 0–6, 12-20
see also individual execution units
channels, 12-91
controller arbitration, 12-106
registers, 12-110–12-112
format, 12-21
gather operation (reading data), 12-17, 12-97
scatter operation (writing data), 12-17, 12-97
algorithm selection, 12-52
endian (byte ordering) considerations, 12-60, 12-61,
recommended settings for mode register, 12-53
architecture, 12-2
execution units (EUs), 12-5
security channels, 12-8
security controller access types, 12-9
Chinese remainder theorem and RSA algorithm, 12-6
elliptic curve operations, 12-5
modular exponentiation operations, 12-6
Montgomery modular multiplication algorithm, 12-6
parameter memories A, B, E, and N, 12-32
dump context mode, 12-42
host-provided context via prevent permute, 12-42
12-33
descriptor types, 12-19
EU selection, 12-18
writeback format, 12-94
descriptor types and formats, 12-24
arbitration of internal buses, 12-105
assignment of EUs to channels, 12-104
crypto-channel states, 12-98
priority arbitration, 12-104, 12-105
12-62
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Serial data/clock, see I
Signals
register descriptions
reset channel, 12-103
transactions (internal)
clock
complete signal listing
DDR
DMA
AESU, 12-67–12-79
AFEU, 12-42–12-50
by acronym, see Register Index
controller registers, 12-109–12-115
crypto-channel, 12-92–12-102
DEU, 12-33–12-41
interrupt registers, 12-110–12-112
KEU, 12-80–12-91
MDEU, 12-50–12-62
PKEU, 12-26–12-32
RNG, 12-63–12-67
master reads, 12-107
master writes, 12-107
slave reads and writes, 12-107
RTC (real time clock), 4-3, 4-23, 10-25, 10-26, 19-29
SYSCLK (system clock input), 4-3
alphabetical reference, 3-10
configuration signals, sampled at POR, 3-15
figure showing groupings, 3-1
output signal states at power-on reset, 3-17
reference by functional block, 3-5
MA[0:14] (address bus), 9-7
MBA[0:1] (logical bank address), 9-7
MCAS (column address strobe), 9-7
MCK[0:5] (DDR clock output complements), 9-9
MCK[0:5] (DDR clock outputs), 9-9
MCKE[0:3] (DDR clock enables), 9-9
MCS[0:3] (chip selects), 9-8
MDIC[0:1] (driver impedance calibration), 9-8
MDM[0:8] (SDRAM data output mask), 9-8
MDQS[0:8] (data bus strobes), 9-6, 9-42
MDVAL (debug mode data valid), 4-20, 21-3, 21-6
MECC[0:5] (error correcting code)
MECC[0:7] (error correcting code), 4-20, 9-6
MODT[0:3] (on-die termination), 9-8
MRAS (row address strobe), 9-7
MSRCID[0:4] (debug source ID), 4-20, 21-3, 21-7
MWE (write enable), 9-8
DMA_DACK[0:3] (DMA acknowledge), 16-6
DMA_DDONE[0:3] (DMA done), 16-6
DMA_DREQ[0:3] (DMA request), 16-6
see also Power-on reset (POR)
as debug signals, 21-3, 21-7
2
C interface, 11-1
Freescale Semiconductor
Index