MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 775

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

TR03WT has no effect. A description of how queue weights affect eTSEC’s round-robin algorithm
appears in
describes the TR03WT register.
Table 15-20
15.5.3.2.7
When modified weighted round-robin Tx scheduling is enabled (TCTRL[TXSCHED] = 10), this register
determines the weighting applied to each enabled transmit queue for queues 4 to 7. For priority-based
scheduling, TR47WT has no effect. A description of how queue weights affect eTSEC’s modified
weighted round-robin algorithm appears in
Queuing (MWRR).” Figure 15-17
Freescale Semiconductor
16–23 WT2 Weighting value for TxBD ring 2 when TCTRL[TXSCHED] = 10. On each round of the Tx scheduler, a minimum
24–31 WT3 Weighting value for TxBD ring 3 when TCTRL[TXSCHED] = 10. On each round of the Tx scheduler, a minimum
Offset eTSEC1:0x2_4144; eTSEC3:0x2_6144
Reset
8–15
Bits Name
0–7
Offset eTSEC1:0x2_4140; eTSEC3:0x2_6140
Reset
W
R
W
R
WT0 Weighting value for TxBD ring 0 when TCTRL[TXSCHED] = 10. On each round of the Tx scheduler, a minimum
WT1 Weighting value for TxBD ring 1 when TCTRL[TXSCHED] = 10. On each round of the Tx scheduler, a minimum
0
0
Section 15.6.5.2.2, “Modified Weighted Round-Robin Queuing (MWRR).” Figure 15-16
of WT0 × 64 bytes of data are scheduled for transmission from TxBD ring 0. Clearing this field prevents
transmission.
of WT1 × 64 bytes of data are scheduled for transmission from TxBD ring 1. Clearing this field prevents
transmission.
of WT2 × 64 bytes of data are scheduled for transmission from TxBD ring 2. Clearing this field prevents
transmission.
of WT3 × 64 bytes of data are scheduled for transmission from TxBD ring 3. Clearing this field prevents
transmission.
describes the fields of the TR03WT register.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
TxBD Ring 4–7 Weighting Register (TR47WT)
WT4
WT0
7
7
8
Figure 15-16. TR03WT Register Definition
Figure 15-17. TR47WT Register Definition
Table 15-20. TR03WT Field Descriptions
8
describes the definition for the TR47WT register.
WT5
WT1
Section 15.6.5.2.2, “Modified Weighted Round-Robin
All zeros
All zeros
15 16
Description
15 16
WT6
WT2
Enhanced Three-Speed Ethernet Controllers
23 24
23 24
Access: Read/Write
Access: Read/Write
WT7
WT3
15-45
31
31