MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 701

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

the transceiver starts to drive those signals after its t
ensure, that [t
14.5.2.3
Principally, a read-modify-write cycle is a read cycle immediately followed by a write cycle. Because the
write cycle will have a new address phase in any case, this basically is the same case as an address phase
after a previous read.
14.5.2.4
The flexibility of the UPM allows the user to insert additional address phases during read cycles by
changing the AMX field, therefore, turning around the bus during one pattern. The LBC automatically
inserts a single bus turnaround cycle if the bus (LAD) was previously high impedance for any reason, such
as a read, before LALE is driven and LAD is driven with the new address. The turnaround cycle is not
inserted on a write, because the bus was already driven to begin with.
However, bus contention could potentially still occur on the far side of a bus transceiver. It is the
responsibility of the designer of the UPM pattern to guarantee that enough idle cycles are inserted in the
UPM pattern to avoid this.
14.5.3
The LBC supports 8-, 16-, and 32-bit data port sizes. However, the bus requires that the portion of the data
bus used for a transfer to or from a particular port size be fixed. A 32-bit port must reside on D[0:31], a
16-bit port must reside on D[0:15], and an 8-bit port must reside on D[0:7]. The local bus always tries to
transfer the maximum amount of data on all bus cycles.
Freescale Semiconductor
Interface to Different Port-Size Devices
en
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
(LB) + t
Read-Modify-Write Cycle for Parity Protected Memory Banks
UPM Cycles with Additional Address Phases
en
(transceiver)] is larger than t
en
(transceiver) time. The system designer has to
dis
(LB) to avoid bus contention.
Local Bus Controller
14-83