MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 618

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

DUART
When the interrupts are disabled in UIER, polling software can not use UIIR[0] to determine whether the
UART is ready for service. The software must monitor the appropriate bits in the line status (ULSR) and/or
the modem status (UMSR) registers. UIIR[0] can be used for polling if the interrupts are enabled in UIER.
13.5
The following requirements must be met for DUART accesses:
A system reset puts the DUART registers to a default state. Before the interface can transfer serial data,
the following initialization steps are recommended:
13-24
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1. Update the programmable interrupt controller (PIC) DUART channel interrupt vector source
2. Set data attributes and control bits in the ULCR, UFCR, UAFR, UMCR, UDLB, and UDMB.
3. Set the data attributes and control bits of the external modem or peripheral device.
4. Set the interrupt enable register (UIER).
5. To start a write transfer, write to the UTHR.
6. Poll UIIR if the interrupts generated by the DUART are masked.
All DUART registers must be mapped to a cache-inhibited and guarded area. (That is, the WIMG
setting in the MMU needs to be 0b01X1.)
All DUART registers are 1 byte wide. Reads and writes to these registers must be byte-wide
operations.
registers.
DUART Initialization/Application Information
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Freescale Semiconductor