MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 296

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

L2 Look-Aside Cache/SRAM
7.6.1
L2 cache coherency rules are as follows:
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The L2 is non-inclusive of the L1—valid L1 lines may be valid or invalid in the L2.
The L2 cache holds no modified data. Data is in one of four states—invalid, exclusive, exclusive
locked, and stale.
The L2 allocates entries for data cast out or pushed (non-global, non-write-through write with kill)
from the L1 caches.
Lines for e500 core-initiated burst read transactions are allocated as exclusive in the L2.
The L2 supports I/O devices reading data from valid lines in the L2 cache (data intervention) if
L2CTL[L2INTDIS] = 0. An optional unlock attribute causes I/O reads to clear a lock when the read
is performed.
The L2 cache does not respond to cache-inhibited read transactions.
e500 core-initiated, cache-inhibited store transactions invalidate the line when they hit on a valid
L2 line. If the line is locked, it goes to the stale state. For other write transactions the
cache-inhibited bit is ignored.
Non-burst cacheable write transactions from the e500 core (generated by write-through cacheable
stores) update a valid L2 cache line through a read-modify-write operation.
e500 core cast out transactions that hit on a stale line in the L2 cache cause a data update of the line
and a change to the valid locked state for that line.
An e500 core-initiated, cacheable, non-write-through store that misses in the L1 and hits on a line
in the L2 invalidates that line in the L2. If the line is marked exclusive locked, the L2 marks the
line as stale.
Transactions that hit a stale L2 cache line that would cause an allocate if they miss cause a data
update of the line (when data arrives from memory) and a change to the line’s valid locked state.
Data is not supplied by the L2 cache for the read in this case.
The following transactions kill the data and the respective locks when they hit a valid L2 line:
— dcbf
— dcbi
The L2 cache supports mixed cache external writes and core-initiated writes to the same addresses
if the core-initiated writes are marked coherency-required, caching allowed, not write-through
(WIMG = 001x) and the external writes are marked coherency-required, caching-allowed.
The L2 cache supports writes to the L2 cache from peripheral devices or from I/O controllers
through snoop write transactions with addresses that hit in a programmed memory range. Full
cache line (32-byte) write transactions update the data for a valid line in the L2 and if the line is
not valid in the L2, a line is allocated. Sub-cache line write transactions update the data only for
valid L2 cache lines through read-modify-write operations.
The L2 cache supports burst writes that lock an L2 cache line from peripheral devices or from I/O
controllers through write transactions with addresses that hit in a programmed memory range that
has the lock attribute set.
L2 Cache Coherency Rules
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Freescale Semiconductor