MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 757

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Freescale Semiconductor
17–19
25–27
Bits
20
21
22
23
24
28
29
30
31
MMWR MII management write completion
MMRD
GRSC
Name
PERR
MAG
DPE
RXF
FIQ
FIR
—
—
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reserved
Magic Packet detected when the eTSEC is in Magic Packet detection mode (MACCFG2[MPEN] = 1).
0 No Magic Packet received, or Magic Packet mode was not enabled.
1 A Magic Packet was received while in Magic Packet mode. MACCFG2[MPEN] is also cleared upon
MII management read completion
0 MII management read not issued or in process.
1 MII management read completed that was initiated by a user through the MII Scan or Read cycle
0 MII management write not issued or in process.
1 MII management write completed that was initiated by a user write to the MIIMCON register.
the user to know if the system has completed the stop and it is safe to write to receive registers (status,
control or configuration registers) that are used by the system during normal operation.
0 Graceful stop not completed.
1 Graceful stop completed.
(RxBD) in that frame was updated. This occurs either if the I (interrupt) bit in the buffer descriptor status word
is set, or an overrun error occurs. The specific receive queue that was updated has its RXF bit set in RSTAT.
0 Frame not received.
1 Frame received.
Reserved
The receive queue filer result is invalid, either because not enough time between frames was available to
find a matching rule, or no entry in the filer table could be matched.
0 Receive queue filer reached a definite result; however, bit FIQ may still be set if a frame was filed to a
1 Receive queue filer was unable to reach a definite result. In this case, bit FIQ will also be set if no entry
Filed frame to invalid receive queue. This bit indicates that either the receive queue filer chose to DMA a
received frame to a disabled RxBD ring, or that no rule in the filer table could be matched.
0 Received frames filed to valid queues or rejected. Note that a frame may be rejected if the filer has
1 Received frames filed to RxBD rings that are not enabled. The frame is discarded. If bit FIR is also set
which is likely to compromise the validity of recently transferred frames.
0 No parity errors detected.
1 Data held in the FIFO or filer arrays is expected to be corrupted due to a parity error.
unambiguously, due to encapsulated header type fields contradicting each other.
0 Received frame parsed successfully.
1 Received frame parse revealed header inconsistencies.
Graceful receive stop complete. This interrupt is asserted if a graceful receive stop is completed. It allows
Receive frame interrupt. This bit indicates that a frame was received and the last receive buffer descriptor
Internal data parity error. This bit indicates that the eTSEC has detected a parity error on its stored data,
Receive frame parse error for TCP/IP off-load. This bit indicates that a received frame could not be parsed
receiving the Magic Packet.
command.
disabled RxBD ring.
in the filer table could provide a rule match.
insufficient time to reach a conclusive result between frames, in which case bit FIR is set.
this indicates that the filer exhausted all of its table entries without a rule match.
Table 15-7. IEVENT Field Descriptions (continued)
Description
Enhanced Three-Speed Ethernet Controllers
15-27