MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 229

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

1
6.5.2
6.5.3
Freescale Semiconductor
55–57
62–63
Reset
Reset
Bits
SPR 286
An MSR bit that is reserved may be altered by a return from interrupt instruction.
SPR 287
54
58
59
60
61
W
W
R
R
32
32
Name
PMM Performance monitor mark bit. System software can set PMM when a marked process is running to enable
DE
DS
—
IS
—
—
Debug interrupt enable. See the description of the DBSR[UDE] in
(DBSR).”
0 Debug interrupts are disabled.
1 Debug interrupts are enabled if DBCR0[IDM] = 1.
Reserved, should be cleared.
Instruction address space
0 The processor directs all instruction fetches to address space 0 (TS = 0 in the relevant TLB entry).
1 The processor directs all instruction fetches to address space 1 (TS = 1 in the relevant TLB entry).
Data address space
0 The processor directs data memory accesses to address space 0 (TS = 0 in the relevant TLB entry).
1 The processor directs data memory accesses to address space 1 (TS = 1 in the relevant TLB entry).
Reserved, should be cleared.
statistics to be gathered only during execution of the marked process. MSR[PR] and MSR[PMM] together define
a state that the processor (supervisor or user) and the process (marked or unmarked) may be in at any time. If
this state matches an individual state specified in the PMLCax, the state for which monitoring is enabled,
counting is enabled.
Preserved for OEA-defined RI and LE, respectively
Processor ID Register (PIR)
Processor Version Register (PVR)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
SoC-dependent value. See
Version
Table 6-6. MSR Field Descriptions (continued)
Figure 6-8. Processor Version Register (PVR)
Figure 6-7. Processor ID Register (PIR)
1
1
Section 5.2, “e500 Processor and System Version Numbers.”
Processor ID
All zeros
47 48
Description
Section 6.13.2, “Debug Status Register
Revision
Access: Supervisor read only
Access: Supervisor read only
Core Register Summary
6-13
63
63