MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 108
MPC8533EVTARJ
Manufacturer Part Number
MPC8533EVTARJ
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8533VTALF.pdf
(112 pages)
2.MPC8533VTALF.pdf
(2 pages)
3.MPC8533VTALF.pdf
(16 pages)
4.MPC8533VTALF.pdf
(1332 pages)
Specifications of MPC8533EVTARJ
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
1.067GHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Available stocks
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- MPC8533VTALF PDF datasheet
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Overview
1-10
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Seven-stage pipeline control
Instruction unit
— Twelve-entry instruction queue
— Full hardware detection of interlocks
— Dispatch of up to two instructions per cycle
— Dispatch serialization control
— Register dependency resolution and renaming
Branch unit (BU)
— Dynamic branch prediction
— Two-entry branch instruction queue (BIQ)
— Executes all branch and CR logical instruction
Completion unit
— As many as 14 instructions allowed in 14-entry completion queue
— In-order retirement of up to two instructions per cycle
— Completion and refetch serialization control
— Synchronization for all instruction flow changes—interrupts and mispredicted branches
Two simple execution units that perform:
— Single-cycle add and subtract
— Single-cycle shift and rotate
— Single-cycle logical operations
— Supports integer signal processing operations
Multiple-cycle execution unit (MU)
— 4-cycle latency for integer and floating-point multiplication (including integer, fractional, and
— Variable-latency divide: 4, 11, 19, and 35 cycles for all Book E, SPE, and embedded
— 4-cycle floating-point multiply
— 4-cycle floating-point add and subtract
Double-precision floating-point APU
Signal processing engine APU (SPE APU). The single instruction multiple data (SIMD) capability
provided by the 64-bit execution units (MIU, LSU, SIU1) is not a separate execution unit. The
hardware that executes 32-bit Book E instructions also executes the lower half of 64-bit SPE APU
instructions.
— Single-cycle integer add and subtract
— Single-cycle logical operations
— Single-cycle shift and rotate
both vector and scalar floating-point multiply instructions)
floating-point divide instructions. Note that the MU allows divide instructions to bypass the
second two MU pipeline stages, freeing those stages for other MU instructions to execute in
parallel.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Freescale Semiconductor
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