MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 1251

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Multi-level triggers can be created using the watchpoint monitor, the performance monitor, and the trace
buffer combined. For example, the WM can be programmed to trigger on events that also increment a PM
counter (the performance monitor must also be programmed to respond to this event), the output of which
(perfmon_overflow) could trigger the start of tracing in the trace buffer.
21.4.5
The trace buffer is a 256 × 64 array that can capture information about the internal processing of
transactions to selected interfaces. The trace buffer controls are a superset of those for the watchpoint
monitor. Close inspection of the trace buffer control registers (TBCRn) and the WM control registers
(WMCRn) shows that trace buffer controls not needed for the WM are marked reserved in WMCRn. This
permits using the trace buffer as a second watchpoint monitor by simply ignoring the trace options.
The trace buffer provides great flexibility about when to start tracing, when to stop tracing, and what to
trace. The trace mode field, TBCR0[MODE], indicates when to trace: on every valid cycle, on a
watchpoint monitor event, or when all the programmed events in the TBCR are met. This permits a user
to program the trace condition in the watchpoint monitor and to program a start or stop condition in the
trace buffer control register. The user can also program the TBCR with the conditions in which to stop
tracing: on an event, or when the buffer is full. TBCR0[IFSEL] specifies which interface transactions are
being captured.
The trace buffer can be programmed to trace the dispatch bus from any of the following:
Transactions come into the ECM, arbitrate for common resources, and get dispatched to the target port.
Information such as transaction types, source ID, and other attributes can be captured in any of the selected
interfaces.
21.4.5.1
Figure 21-20
when TBCR1[IFSEL] = 000.
Freescale Semiconductor
Reset
W
R
•
•
•
CMDTT CMDSID CMDTID CMDBC
e500 coherency module (ECM)
Outbound host interface to the PCI controller
Host interface to the DDR controller
0
Trace Buffer
4
Traced Data Formats (as a Function of TBCR1[IFSEL])
shows the trace buffer entry format for an ECM dispatch (CMD) transaction that is specified
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
5
Figure 21-20. e500 Coherency Module Dispatch (CMD) Trace Buffer Entry
9
10
13
14
18
19
—
31
All zeros
32
Debug Features and Watchpoint Facility
CMDADDR
21-27
63