MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 328

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

DDR Memory Controller
9-6
MDQS[0:8]/
MDQS[0:8]
MECC[0:7]
Signal
Table 9-3. Memory Interface Signals—Detailed Signal Descriptions (continued)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
I/O
I/O Data strobes. Inputs with read data, outputs with write data. The data strobes may be single ended or
I/O Error checking and correcting codes. Input and output signals for the DDR controller’s bidirectional ECC
O
O
I
I
differential.
As outputs, the data strobes are driven by the DDR memory controller during a write transaction. The
memory controller always drives these signals low unless a read has been issued and incoming data
strobes are expected. This keeps the data strobes from floating high when there are no transactions on
the DRAM interface.
As inputs, the data strobes are driven by the external DDR SDRAMs during a read transaction. The data
strobes are used by the memory controller to synchronize data latching.
bus. MECC[0:5] function in both normal and debug modes.
As normal mode outputs the ECC signals represent the state of ECC driven by the DDR controller on
writes. As debug mode outputs MECC[0:5] provide source ID and data-valid information. See
Section 9.5.11, “Error Checking and Correcting
ECC Pins,”
As inputs, the ECC signals represent the state of ECC driven by the SDRAM devices on reads.
Meaning
Meaning
Meaning
Meaning
Timing Assertion/Negation—If a WRITE command is registered at clock edge n , data strobes at the
Timing Assertion/Negation—If a READ command is registered at clock edge n , and the latency is
Timing Assertion/Negation—Same timing as MDQ
Timing Assertion/Negation—Same timing as MDQ
State
State
State
State
Asserted/Negated—Driven high when positive capture data is transmitted and driven low
Asserted/Negated—Driven high when positive capture data is received and driven low when
Asserted/Negated—Represents the state of ECC being driven by the DDR controller on
High impedance—Same timing as MDQ
Asserted/Negated—Represents the state of ECC being driven by the DDR SDRAMs on
High impedance—Same timing as MDQ
for more details.
when negative capture data is transmitted. Centered in the data “eye” for writes;
coincident with the data eye for reads. Treated as a clock. Data is valid when signals
toggle. See
DRAM assert centered in the data eye on clock edge n + 1 . See the JEDEC DDR
SDRAM specification for more information.
negative capture data is received. Centered in the data eye for writes; coincident with
the data eye for reads. Treated as a clock. Data is valid when signals toggle. See
Table 9-38
programmed in TIMING_CFG_1[CASLAT] to be m clocks, data strobes at the DRAM
assert coincident with the data on clock edge n + m . See the JEDEC DDR SDRAM
specification for more information.
writes.
reads.
for byte lane assignments.
Table 9-38
for byte lane assignments.
Description
(ECC),” and
Section 21.4.2.2, “Debug Information on
Freescale Semiconductor