MPC8533EVTARJ Freescale Semiconductor, MPC8533EVTARJ Datasheet - Page 802

• Manufacturer Part Number: MPC8533EVTARJ
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTARJ

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.067GHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Enhanced Three-Speed Ethernet Controllers
15.5.3.5.5
The MAXFRM register is written by the user.
Table 15-43
15.5.3.5.6
The MIIMCFG register is written by the user to configure all MII management operations. Note that MII
management hardware is shared by all eTSECs. Thus, only through the MIIM registers of eTSEC1 can
external PHYs be accessed and configured. Note: when an eTSEC is configured to use TBI/RTBI,
configuration of the TBI/RTBI (described in
MIIM registers for that eTSEC. For example, if a TBI/RTBI interface is required on eTSEC3, then the
MIIM registers starting at offset 0x2_6520 are used to configure it.
Figure 15-41
15-72
16–31 Maximum Frame By default this field is set to 0x0600 (1536 bytes). It sets the maximum Ethernet frame size in both
0–15
Bits
Offset
Reset 0
Offset eTSEC1:0x2_4520
Reset
W
R
W
R
0
Reset Mgmt
eTSEC1:0x2_4510; eTSEC3:0x2_6510
Name
0
describes the fields of the MAXFRM register.
describes the definition for the MIIMCFG register.
—
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
0
0
Maximum Frame Length Register (MAXFRM)
MII Management Configuration Register (MIIMCFG)
0
0
Figure 15-41. MII Management Configuration Register Definition
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1
Reserved
the transmit and receive directions. (Refer to MACCFG2[Huge Frame].). It does not affect the size of
packets sent or received via the FIFO packet interface.
Note that if MACCFG2[Huge Frame] = 0, the value of this field must be less than or equal to
MRBLR[MRBL] × (minimum number of RxBDs per ring). See
Configuration 2 Register
Register
Figure 15-40. Maximum Frame Length Register Definition
0
0
(MRBLR),” and
0
—
0
Table 15-43. MAXFRM Descriptions
0
0
0
Section 15.6.7.3, “Receive Buffer Descriptors
(MACCFG2),”
Section 15.5.4, “Ten-Bit Interface
0
Figure 15-40
0
0
—
15 16
0
Section 15.5.3.3.9, “Maximum Receive Buffer Length
0
Description
shows the MAXFRM register.
0
0
0
0
1
Section 15.5.3.5.2, “MAC
Maximum Frame
1
0
(TBI)”) is done via the
(RxBD).”
0
26
0
Freescale Semiconductor
0
No Pre — MgmtClk
27
0
0
Access: Read/Write
Access: Read/Write
0
28 29
0
0
1
0
1
0
31
31
0
1