OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 132

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
8.3.3 GPIO pin output register
8.3.4 GPIO pin output set register
pin may have GPIO input, GPIO output, and counter/timer match output and capture input
as selectable functions. Through the PIN register, the current logic state of the pin can be
read in any configuration, e.g. the state of the capture input could be read.
As an exception, the pin state cannot be read if its analog function is selected (if
applicable) because selecting the pin as an ADC input disconnects the digital features of
the pin. In that case, the pin value read in the PIN register is not valid.
Note that read operations are masked by the MASK bits. Read operations on masked bits
always return 0 regardless of the pin’s actual level.
Table 123. GPIO pin value register (PIN - address 0x5000 0004 (GPIO0), 0x5001 0004 (GPIO1);
Writing 0 or 1 to this register produces LOW or HIGH levels at the corresponding port
pins. The port pin is set to this value if it is configured as GPIO output. For all other
configurations (input, non-GPIO function), the value of the OUT register bit has no effect
on the pin output level. Write operations are masked by the MASK registers.
Reading this register returns the contents of the GPIO output register regardless of the
digital pin configuration and direction. Read operations are masked by the MASK
registers.
The SET, CLR, and NOT registers write to the OUT register to allow bit-wise setting,
clearing, and inverting of individual port pins. The port output state is determined by the
contents of the OUT register only.
Table 124. GPIO pin output register (OUT - address 0x5000 0008 (GPIO0), 0x5001 0008
This register is used to produce a HIGH level output at the port pins configured as GPIO
output in the DIR register (see
register (see
no effect on the GPIO output level. If a pin is not configured as GPIO and output, the SET
register has no effect on the pin level.
This register is a write-only register. Note that write operations to the SET register are
masked by the MASK register.
Bit
31:0
Bit
31:0
Symbol Description
OUT
Symbol
PIN
0x5002 0004 (GPIO2)) bit description
(GPIO1), 0x5002 0008 (GPIO2)) bit description
Table
All information provided in this document is subject to legal disclaimers.
GPIO pin PIOn_x output value.
0 = Write: Set GPIO output pin to LOW. Read: GPIO output
value is LOW.
1 = Write: Set GPIO output pin to HIGH. Read: GPIO output
value is HIGH.
Description
0 = Digital pin level is LOW. 1 = Digital pin level is HIGH.
GPIO pin PIOn_x value.
60). Writing 1 sets the corresponding port pin to HIGH. Writing 0 has
Rev. 1 — 15 February 2011
Table
128) and as GPIO in the corresponding IOCONFIG
Chapter 8: LPC122x General Purpose I/O (GPIO)
UM10441
© NXP B.V. 2011. All rights reserved.
Reset
value
0x0
Reset
value
0x00
Access
R
Access
R/W
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