OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 374

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
25.3.4.1 Lockup
25.3.4 Fault handling
not a normal branch operation and, instead, that the exception is complete. Therefore, it
starts the exception return sequence. Bits[3:0] of the EXC_RETURN value indicate the
required return stack and processor mode, as
Table 362. Exeption return behavior
Faults are a subset of exceptions, see
exception being taken or cause lockup if they occur in the NMI or HardFault handler. The
faults are:
Only Reset and NMI can preempt the fixed priority HardFault handler. A HardFault can
preempt any exception other than Reset, NMI, or another hard fault.
The processor enters a lockup state if a fault occurs when executing the NMI or HardFault
handlers, or if the system generates a bus error when unstacking the PSR on an
exception return using the MSP. When the processor is in lockup state it does not execute
any instructions. The processor remains in lockup state until one of the following occurs:
EXC_RETURN
0xFFFFFFF1
0xFFFFFFF9
0xFFFFFFFD
All other values
•
•
•
•
•
•
•
•
•
•
•
•
execution of an SVC instruction at a priority equal or higher than SVCall
execution of a BKPT instruction without a debugger attached
a system-generated bus error on a load or store
execution of an instruction from an XN memory address
execution of an instruction from a location for which the system generates a bus fault
a system-generated bus error on a vector fetch
execution of an Undefined instruction
execution of an instruction when not in Thumb-State as a result of the T-bit being
previously cleared to 0
an attempted load or store to an unaligned address.
it is reset
a debugger halts it
an NMI occurs and the current lockup is in the HardFault handler.
All information provided in this document is subject to legal disclaimers.
Description
Return to Handler mode.
Exception return gets state from the main stack.
Execution uses MSP after return.
Return to Thread mode.
Exception return gets state from MSP.
Execution uses MSP after return.
Return to Thread mode.
Exception return gets state from PSP.
Execution uses PSP after return.
Reserved.
Rev. 1 — 15 February 2011
Section
Chapter 25: LPC122x Appendix ARM Cortex-M0
Table 25–362
25–25.3.3. All faults result in the HardFault
shows.
UM10441
© NXP B.V. 2011. All rights reserved.
374 of 442