OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 187
OM13013,598
Manufacturer Part Number
OM13013,598
Description
BOARD DEMO IAR LPC1227 JLINKLITE
Manufacturer
NXP Semiconductors
Series
-r
Specifications of OM13013,598
Design Resources
LPC122x-SK Brd Schematic
Processor To Be Evaluated
LPC1227
Processor Series
LPC122x
Data Bus Width
32 bit
Interface Type
UART, SSP, SPI, I2C
Cpu Core
ARM Cortex-M0
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
3 V to 3.6 V
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-6885
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NXP Semiconductors
UM10441
User manual
11.7.6 I
11.7.7 I
I2SCLL and I2SCLH values should not necessarily be the same. Software can set
different duty cycles on SCL by setting these two registers. For example, the I
specification defines the SCL low time and high time at different values for a Fast-mode
and Fast-mode Plus I
The I2CONCLR registers control clearing of bits in the I2CON register that controls
operation of the I
corresponding bit in the I
Table 189. I
AAC is the Assert Acknowledge Clear bit. Writing a 1 to this bit clears the AA bit in the
I2CONSET register. Writing 0 has no effect.
SIC is the I
register. Writing 0 has no effect.
STAC is the START flag Clear bit. Writing a 1 to this bit clears the STA bit in the
I2CONSET register. Writing 0 has no effect.
I2ENC is the I
I2CONSET register. Writing 0 has no effect.
This register controls the Monitor mode which allows the I
the I
Bit Symbol
1:0 -
2
3
4
5
6
7
31:
8
2
2
C Control Clear register (CONCLR - 0x4000 0018)
C Monitor mode control register
2
AAC
SIC
-
STAC
I2ENC
-
-
C bus without actually participating in traffic or interfering with the I
2
2
C Interrupt Clear bit. Writing a 1 to this bit clears the SI bit in the I2CONSET
C Control Clear register (CONCLR - 0x4000 0018) bit description
2
C Interface Disable bit. Writing a 1 to this bit clears the I2EN bit in the
All information provided in this document is subject to legal disclaimers.
Description
Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Assert acknowledge Clear bit.
I
Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
START flag Clear bit.
I
Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Reserved
2
2
2
C interface. Writing a one to a bit of this register causes the
C interrupt Clear bit.
C interface Disable bit.
2
Rev. 1 — 15 February 2011
C.
2
C control register to be cleared. Writing a zero has no effect.
Chapter 11: LPC122x I2C-bus controller
2
C module to monitor traffic on
UM10441
© NXP B.V. 2011. All rights reserved.
2
C bus.
2
C-bus
Reset
value
NA
NA
0
0
NA
-
0
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