OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 410

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
Table 375. CMISIS acess NVIC functions
[1]
UM10441
User manual
CMSIS function
void NVIC_EnableIRQ(IRQn_Type IRQn)
void NVIC_DisableIRQ(IRQn_Type IRQn)
void NVIC_SetPendingIRQ(IRQn_Type IRQn)
void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
uint32_t NVIC_GetPriority(IRQn_Type IRQn)
The input parameter IRQn is the IRQ number, see
25.5.2.1 Accessing the Cortex-M0 NVIC registers using CMSIS
25.5.2.2 Interrupt Set-enable Register
25.5.2.3 Interrupt Clear-enable Register
CMSIS functions enable software portability between different Cortex-M profile
processors.
To access the NVIC registers when using CMSIS, use the following functions:
The ISER enables interrupts, and shows which interrupts are enabled. See the register
summary in
The bit assignments are:
Table 376. ISER bit assignments
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an
interrupt is not enabled, asserting its interrupt signal changes the interrupt state to
pending, but the NVIC never activates the interrupt, regardless of its priority.
The ICER disables interrupts, and show which interrupts are enabled. See the register
summary in
The bit assignments are:
Bits
[31:0]
SETENA
Name
Table 374
Table 25–374
[1]
[1]
All information provided in this document is subject to legal disclaimers.
[1]
[1]
[1]
Table 361
Rev. 1 — 15 February 2011
for the register attributes.
[1]
Function
Interrupt set-enable bits.
Write:
0 = no effect
1 = enable interrupt.
Read:
0 = interrupt disabled
1 = interrupt enabled.
for the register attributes.
[1]
for more information.
Description
Enables an interrupt or exception.
Disables an interrupt or exception.
Sets the pending status of interrupt or exception to 1.
Clears the pending status of interrupt or exception to 0.
Reads the pending status of interrupt or exception.
This function returns non-zero value if the pending status is set
to 1.
Sets the priority of an interrupt or exception with configurable
priority level to 1.
Reads the priority of an interrupt or exception with configurable
priority level. This function returns the current priority level.
Chapter 25: LPC122x Appendix ARM Cortex-M0
UM10441
© NXP B.V. 2011. All rights reserved.
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