OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 54

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
4.10.4.1 Normal mode
4.10.4 Frequency selection
The PLL frequency equations use the following parameters (also see
Table 53.
In normal mode the post divider is enabled, giving a 50% duty cycle clock with the
following frequency relations:
To select the appropriate values for M and P, it is recommended to follow these steps:
Table 54.
Parameter
FCLKIN
FCCO
FCLKOUT
P
M
PLL input
clock
sys_pllclkin
(Fclkin)
12 MHz
12 MHz
12 MHz
1. Specify the input clock frequency Fclkin.
2. Calculate M to obtain the desired output frequency Fclkout with M = F
3. Find a value so that FCCO = 2 × P × F
4. Verify that all frequencies and divider values conform to the limits specified in
5. Ensure that FCLKOUT < 100 MHz.
Table
10.
PLL frequency parameters
PLL configuration examples
Main clock
(Fclkout)
<tbd>
<tbd>
24 MHz
All information provided in this document is subject to legal disclaimers.
System PLL
Frequency of sys_pllclkin (input clock to the system PLL) from the
SYSPLLCLKSEL multiplexer (see
Frequency of the Current Controlled Oscillator (CCO); 156 to 320 MHz.
Frequency of sys_pllclkout. FCLKOUT must be < 100 MHz.
System PLL post divider ratio; PSEL bits in SYSPLLCTRL (see
System PLL feedback divider register; MSEL bits in SYSPLLCTRL (see
Section
Fclkout
Rev. 1 — 15 February 2011
4.5.3).
MSEL bits
Table 10
<tbd>
<tbd>
00001 (binary)
=
M
×
Fclkin
Chapter 4: LPC122x System control (SYSCON)
clkout
M divider
value
<tbd>
<tbd>
2
=
(
.
FCCO
Section
PSEL bits
Table 10
<tbd>
<tbd>
10 (binary)
)
⁄
(
4.5.9).
2
×
P
)
P divider
value
<tbd>
<tbd>
4
Figure
UM10441
© NXP B.V. 2011. All rights reserved.
clkout
Section
3):
FCCO
frequency
<tbd>
<tbd>
192 MHz
/ F
clkin
54 of 442
4.5.3).
.
(1)