OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 408

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
25.4.7.12.1 Syntax
25.4.7.12.2 Operation
25.4.7.12.3 Restrictions
25.4.7.12.4 Condition flags
25.4.7.11.3 Restrictions
25.4.7.11.4 Condition flags
25.4.7.11.5 Examples
25.4.7.12 WFI
If the event register is 1, WFE clears it to 0 and completes immediately.
For more information see
Remark: WFE is intended for power saving only. When writing software assume that WFE
might behave as NOP.
There are no restrictions.
This instruction does not change the flags.
Wait for Interrupt.
WFI
WFI
Remark: WFI is intended for power saving only. When writing software assume that WFI
might behave as a NOP operation.
There are no restrictions.
This instruction does not change the flags.
suspends execution until one of the following events occurs:
•
•
•
•
•
•
•
an exception, unless masked by the exception mask registers or the current priority
level
an exception enters the Pending state, if SEVONPEND in the System Control
Register is set
a Debug Entry request, if debug is enabled
an event signaled by a peripheral or another processor in a multiprocessor system
using the SEV instruction.
an exception
an interrupt becomes pending which would preempt if PRIMASK was clear
a Debug Entry request, regardless of whether debug is enabled.
WFE ; Wait for event
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 15 February 2011
Section
25–25.3.5.
Chapter 25: LPC122x Appendix ARM Cortex-M0
UM10441
© NXP B.V. 2011. All rights reserved.
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