OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 254

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

14.1 How to read this chapter
14.2 Basic configuration
14.3 Features
14.4 Applications
UM10441
User manual
CT32B0/1 are available on all LPC122x parts.
The peripheral clocks to the 32-bit timer counter blocks are provided by the system clock,
which is controlled by the SYSAHBCLKDIV register
be disabled through the System AHB clock control register bits 9 and 10
power savings.
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UM10441
Chapter 14: LPC122x 32-bit Counter/timer 0/1 (CT32B0/1)
Rev. 1 — 15 February 2011
Two 32-bit counter/timers with a programmable 32-bit prescaler.
Counter or timer operation.
Four 32-bit capture channels that can take a snapshot of the timer value when an
input signal transitions. A capture event may also optionally generate an interrupt.
The timer and prescaler may be configured to be cleared on a designated capture
event. This feature permits easy pulse-width measurement by clearing the timer on
the leading edge of an input pulse and capturing the timer value on the trailing edge.
Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
Four external outputs corresponding to match registers with the following capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
For each timer, up to four match registers can be configured as PWM allowing to use
up to three match outputs as single edge controlled PWM outputs.
Up to two match registers can be used to generate timed DMA requests.
Interval timer for counting internal events
Pulse Width Demodulator via capture input
Free running timer
Pulse Width Modulator via match outputs
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 15 February 2011
(Table
20). The CT32B0/1 blocks can
© NXP B.V. 2011. All rights reserved.
(Table
User manual
21) for
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