OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 403

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
25.4.7.1.2 Operation
25.4.7.1.3 Restrictions
25.4.7.1.4 Condition flags
25.4.7.1.5 Examples
25.4.7.2.1 Syntax
25.4.7.2.2 Operation
25.4.7.2.3 Restrictions
25.4.7.2.4 Condition flags
25.4.7.2.5 Examples
25.4.7.3.1 Syntax
25.4.7.2 CPS
25.4.7.3 DMB
The BKPT instruction causes the processor to enter Debug state. Debug tools can use
this to investigate system state when the instruction at a particular address is reached.
imm is ignored by the processor. If required, a debugger can use it to store additional
information about the breakpoint.
The processor might also produce a HardFault or go in to lockup if a debugger is not
attached when a BKPT instruction is executed. See
information.
There are no restrictions.
This instruction does not change the flags.
Change Processor State.
CPSID i
CPSIE i
CPS changes the PRIMASK special register values. CPSID causes interrupts to be
disabled by setting PRIMASK. CPSIE cause interrupts to be enabled by clearing
PRIMASK.See
There are no restrictions.
This instruction does not change the condition flags.
Data Memory Barrier.
DMB
BKPT #0
CPSID i ; Disable all interrupts except NMI (set PRIMASK)
CPSIE i ; Enable interrupts (clear PRIMASK)
Section 25–25.3.1.3.6
All information provided in this document is subject to legal disclaimers.
; Breakpoint with immediate value set to 0x0.
Rev. 1 — 15 February 2011
for more information about these registers.
Chapter 25: LPC122x Appendix ARM Cortex-M0
Section 25–25.3.4.1
UM10441
© NXP B.V. 2011. All rights reserved.
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