OM13013,598 NXP Semiconductors, OM13013,598 Datasheet - Page 29

• Manufacturer Part Number: OM13013,598
• Description: BOARD DEMO IAR LPC1227 JLINKLITE
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of OM13013,598

• Design Resources: LPC122x-SK Brd Schematic
• Processor To Be Evaluated: LPC1227
• Processor Series: LPC122x
• Data Bus Width: 32 bit
• Interface Type: UART, SSP, SPI, I2C
• Cpu Core: ARM Cortex-M0
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6885

NXP Semiconductors
UM10441
User manual
4.5.28 IRQ latency register
4.5.29 NMI interrupt source configuration register
Table 34.
The IRQLATENCY register is an eight-bit register which specifies the minimum number of
cycles (0-255) permitted for the system to respond to an interrupt request. The intent of
this register is to allow the user to select a trade-off between interrupt response time and
determinism.
Setting this parameter to a very low value (e.g. zero) will guarantee the best possible
interrupt performance but will also introduce a significant degree of uncertainty and jitter.
Requiring the system to always take a larger number of cycles (whether it needs it or not)
will reduce the amount of uncertainty but may not necessarily eliminate it.
Theoretically, the ARM Cortex-M0 core should always be able to service an interrupt
request within 15 cycles. System factors external to the cpu, however, bus latencies,
peripheral response times, etc. can increase the time required to complete a previous
instruction before an interrupt can be serviced. Therefore, accurately specifying a
minimum number of cycles that will ensure determinism will depend on the application.
The default setting for this register is 0x010.
Table 35.
This register configures a source for the ARM Cortex-M0 Non-Maskable Interrupt (NMI).
See
Bit
1:0
3:2
5:4
31:6
Bit
7:0
31:8
Section
Symbol
M0PRIO
DMAPRIO
-
-
Symbol
LATENCY
-
AHB matrix master priority register (AHBPRIO, address 0x4004 8158) bit
description
IRQ latency register (IRQLATENCY, address 0x4004 8170) bit description
25.5.2.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 15 February 2011
Description
Priority of the ARM Cortex-M0 core
Priority of the micro DMA controller
Reserved
Reserved
Description
8-bit latency value
Reserved
Chapter 4: LPC122x System control (SYSCON)
UM10441
© NXP B.V. 2011. All rights reserved.
0x010
-
Reset
value
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Reset
value
00
01
-
-